TWI390736B - 包括在絕緣層上不同厚度之半導體島之電子裝置及其形成之方法 - Google Patents

包括在絕緣層上不同厚度之半導體島之電子裝置及其形成之方法 Download PDF

Info

Publication number
TWI390736B
TWI390736B TW096108232A TW96108232A TWI390736B TW I390736 B TWI390736 B TW I390736B TW 096108232 A TW096108232 A TW 096108232A TW 96108232 A TW96108232 A TW 96108232A TW I390736 B TWI390736 B TW I390736B
Authority
TW
Taiwan
Prior art keywords
semiconductor
layer
semiconductor island
oxidation
island
Prior art date
Application number
TW096108232A
Other languages
English (en)
Chinese (zh)
Other versions
TW200742088A (en
Inventor
沙達卡 馬里安Ｇ
顏 恩古言 畢奇
辛文業
Original Assignee
飛思卡爾半導體公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 飛思卡爾半導體公司 filed Critical 飛思卡爾半導體公司
Publication of TW200742088A publication Critical patent/TW200742088A/zh
Application granted granted Critical
Publication of TWI390736B publication Critical patent/TWI390736B/zh

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/61—Formation of materials, e.g. in the shape of layers or pillars of insulating materials using masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6302—Non-deposition formation processes
    • H10P14/6304—Formation by oxidation, e.g. oxidation of the substrate
    • H10P14/6306—Formation by oxidation, e.g. oxidation of the substrate of the semiconductor materials
    • H10P14/6308—Formation by oxidation, e.g. oxidation of the substrate of the semiconductor materials of Group IV semiconductors
    • H10P14/6309—Formation by oxidation, e.g. oxidation of the substrate of the semiconductor materials of Group IV semiconductors of silicon in uncombined form, i.e. pure silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6302—Non-deposition formation processes
    • H10P14/6322—Formation by thermal treatments

Landscapes

  • Thin Film Transistor (AREA)
  • Element Separation (AREA)
  • Formation Of Insulating Films (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
TW096108232A 2006-03-15 2007-03-09 包括在絕緣層上不同厚度之半導體島之電子裝置及其形成之方法 TWI390736B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/375,893 US7419866B2 (en) 2006-03-15 2006-03-15 Process of forming an electronic device including a semiconductor island over an insulating layer

Publications (2)

Publication Number Publication Date
TW200742088A TW200742088A (en) 2007-11-01
TWI390736B true TWI390736B (zh) 2013-03-21

Family

ID=38518462

Family Applications (1)

Application Number Title Priority Date Filing Date
TW096108232A TWI390736B (zh) 2006-03-15 2007-03-09 包括在絕緣層上不同厚度之半導體島之電子裝置及其形成之方法

Country Status (5)

Country Link
US (1) US7419866B2 (https=)
JP (1) JP5366797B2 (https=)
KR (1) KR20080102388A (https=)
TW (1) TWI390736B (https=)
WO (1) WO2007130728A2 (https=)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7456055B2 (en) 2006-03-15 2008-11-25 Freescale Semiconductor, Inc. Process for forming an electronic device including semiconductor fins
US8815712B2 (en) * 2011-12-28 2014-08-26 Taiwan Semiconductor Manufacturing Company, Ltd. Method for epitaxial re-growth of semiconductor region
US10366884B1 (en) * 2018-11-08 2019-07-30 Stratio Methods for forming a germanium island using selective epitaxial growth and a sacrificial filling layer

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3017860B2 (ja) * 1991-10-01 2000-03-13 株式会社東芝 半導体基体およびその製造方法とその半導体基体を用いた半導体装置
KR100218299B1 (ko) * 1996-02-05 1999-09-01 구본준 트랜지스터 제조방법
US6870225B2 (en) * 2001-11-02 2005-03-22 International Business Machines Corporation Transistor structure with thick recessed source/drain structures and fabrication process of same
JP2003332580A (ja) * 2002-05-09 2003-11-21 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法
US7074623B2 (en) * 2002-06-07 2006-07-11 Amberwave Systems Corporation Methods of forming strained-semiconductor-on-insulator finFET device structures
US6720619B1 (en) * 2002-12-13 2004-04-13 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor-on-insulator chip incorporating partially-depleted, fully-depleted, and multiple-gate devices
US6867433B2 (en) * 2003-04-30 2005-03-15 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor-on-insulator chip incorporating strained-channel partially-depleted, fully-depleted, and multiple-gate transistors
US6909147B2 (en) * 2003-05-05 2005-06-21 International Business Machines Corporation Multi-height FinFETS
US6927146B2 (en) * 2003-06-17 2005-08-09 Intel Corporation Chemical thinning of epitaxial silicon layer over buried oxide
US6911383B2 (en) * 2003-06-26 2005-06-28 International Business Machines Corporation Hybrid planar and finFET CMOS devices
EP1519421A1 (en) 2003-09-25 2005-03-30 Interuniversitair Microelektronica Centrum Vzw Multiple gate semiconductor device and method for forming same
US7301206B2 (en) * 2003-08-01 2007-11-27 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor-on-insulator SRAM configured using partially-depleted and fully-depleted transistors
US7075150B2 (en) * 2003-12-02 2006-07-11 International Business Machines Corporation Ultra-thin Si channel MOSFET using a self-aligned oxygen implant and damascene technique
US7247569B2 (en) * 2003-12-02 2007-07-24 International Business Machines Corporation Ultra-thin Si MOSFET device structure and method of manufacture
JP2005340768A (ja) * 2004-04-26 2005-12-08 Asahi Glass Co Ltd 多値不揮発性半導体記憶素子およびその製造方法
US20050275018A1 (en) * 2004-06-10 2005-12-15 Suresh Venkatesan Semiconductor device with multiple semiconductor layers
US7211474B2 (en) * 2005-01-18 2007-05-01 International Business Machines Corporation SOI device with body contact self-aligned to gate
US7432149B2 (en) * 2005-06-23 2008-10-07 Taiwan Semiconductor Manufacturing Company, Ltd. CMOS on SOI substrates with hybrid crystal orientations

Also Published As

Publication number Publication date
WO2007130728A2 (en) 2007-11-15
KR20080102388A (ko) 2008-11-25
TW200742088A (en) 2007-11-01
US20070218707A1 (en) 2007-09-20
JP2009530828A (ja) 2009-08-27
US7419866B2 (en) 2008-09-02
JP5366797B2 (ja) 2013-12-11
WO2007130728A3 (en) 2008-11-06

Similar Documents

Publication Publication Date Title
TWI397961B (zh) 用以形成包含鰭型結構的電子裝置之製程
JP6931052B2 (ja) 半導体構造体を形成する方法および縦型トランスポートｆｅｔ構造体
CN103283016B (zh) 根据鳍片fet工艺制造电阻器的结构和方法
TWI786298B (zh) 半導體裝置及其製造方法
JP2001298194A (ja) 電界効果型トランジスタ及びその製造方法
CN102460683A (zh) 包含金属栅极与形成于绝缘结构上的含硅电阻器的半导体装置
WO2011079604A1 (zh) 一种半导体器件及其制造方法
JP6076584B2 (ja) 半導体装置及びその製造方法
JP5914865B2 (ja) 半導体装置
JP2005167207A (ja) 薄膜トランジスタ
US20220271129A1 (en) Semiconductor device including fin and method for manufacturing the same
US7456055B2 (en) Process for forming an electronic device including semiconductor fins
WO2014032338A1 (zh) 半导体结构及其制造方法
WO2015118417A1 (en) Metal semiconductor alloy contact resistance improvement
CN111710649B (zh) 一种半导体器件及其制作方法
US7397073B2 (en) Barrier dielectric stack for seam protection
US10636887B2 (en) Self-limiting fin spike removal
TWI390736B (zh) 包括在絕緣層上不同厚度之半導體島之電子裝置及其形成之方法
TWI227362B (en) Liquid crystal display manufacturing process and polysilicon layer forming process
CN102881634A (zh) 半导体器件结构及其制作方法
CN109887845B (zh) 半导体器件及其形成方法
JP2008072142A (ja) 半導体装置の製造方法
CN113948443B (zh) Soi的有源区的隔离方法
CN104916587A (zh) 用于高密度集成电路设计的半导体器件及其制备方法
CN203038895U (zh) 一种半导体结构

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees