JP5366797B2 - 絶縁層の上に厚さの異なる複数の半導体島を含む電子デバイスおよびその形成方法 - Google Patents
絶縁層の上に厚さの異なる複数の半導体島を含む電子デバイスおよびその形成方法 Download PDFInfo
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- JP5366797B2 JP5366797B2 JP2009500541A JP2009500541A JP5366797B2 JP 5366797 B2 JP5366797 B2 JP 5366797B2 JP 2009500541 A JP2009500541 A JP 2009500541A JP 2009500541 A JP2009500541 A JP 2009500541A JP 5366797 B2 JP5366797 B2 JP 5366797B2
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- 239000004065 semiconductor Substances 0.000 title claims description 197
- 238000000034 method Methods 0.000 title claims description 33
- 230000003647 oxidation Effects 0.000 claims description 124
- 238000007254 oxidation reaction Methods 0.000 claims description 124
- 239000000758 substrate Substances 0.000 claims description 38
- 239000000463 material Substances 0.000 claims description 36
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 34
- 229910052760 oxygen Inorganic materials 0.000 claims description 34
- 239000001301 oxygen Substances 0.000 claims description 34
- 238000000059 patterning Methods 0.000 claims description 14
- 150000004767 nitrides Chemical class 0.000 claims description 7
- 230000001590 oxidative effect Effects 0.000 claims description 7
- 239000012212 insulator Substances 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 134
- 125000006850 spacer group Chemical group 0.000 description 15
- 238000000151 deposition Methods 0.000 description 13
- 238000005530 etching Methods 0.000 description 8
- 230000008021 deposition Effects 0.000 description 7
- 238000002955 isolation Methods 0.000 description 6
- 229910052751 metal Inorganic materials 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- 239000000203 mixture Substances 0.000 description 6
- 238000005498 polishing Methods 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 5
- 229910052732 germanium Inorganic materials 0.000 description 5
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 4
- 150000001875 compounds Chemical class 0.000 description 3
- 239000013078 crystal Substances 0.000 description 3
- 239000002019 doping agent Substances 0.000 description 3
- 238000001459 lithography Methods 0.000 description 3
- -1 oxynitride Chemical compound 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 2
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 229910052799 carbon Inorganic materials 0.000 description 2
- 230000005012 migration Effects 0.000 description 2
- 238000013508 migration Methods 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- 229910005742 Ge—C Inorganic materials 0.000 description 1
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000011247 coating layer Substances 0.000 description 1
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000007607 die coating method Methods 0.000 description 1
- 238000010292 electrical insulation Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 229910001092 metal group alloy Inorganic materials 0.000 description 1
- 229910003465 moissanite Inorganic materials 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/32—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
- H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
- H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
- H01L21/02238—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/314—Inorganic layers
- H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
- H01L21/3165—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation
- H01L21/31654—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of semiconductor materials, e.g. the body itself
- H01L21/31658—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of semiconductor materials, e.g. the body itself by thermal oxidation, e.g. of SiGe
- H01L21/31662—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of semiconductor materials, e.g. the body itself by thermal oxidation, e.g. of SiGe of silicon in uncombined form
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Thin Film Transistor (AREA)
- Element Separation (AREA)
- Formation Of Insulating Films (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
用語「横方向の寸法(lateral dimension)」は、物体を参照するとき、物体の平面図から分かる1つの寸法を表す。横方向の寸法には、長さおよび幅が含まれる。長さと幅との間では、幅は長さと同じか、または長さより短い。円の直径は幅であると考えられ、本明細書においては、円は長さを有しない。
Claims (5)
- 電子デバイスの形成方法であって、
パターン形成された第1の耐酸化層を半導体層の上に形成する工程であって、前記半導体層は、基板の上に位置する絶縁体の上に位置する工程と、
半導体層をパターン形成して第1の半導体島および第2の半導体島を形成する工程であって、前記第1の半導体島は第1の表面と、第1の表面に対向する第2の表面とを含み、第1の表面は第2の表面と比較して基板のより近くに位置し、前記第2の半導体島は第3の表面と、第3の表面に対向する第4の表面とを含み、第3の表面は第4の表面と比較して基板のより近くに位置する工程と、
第1の半導体島および第2の半導体島の側面に沿って耐酸化材料をそれぞれ形成する工程と、
第1の耐酸化層、第1の半導体島、第2の半導体島、および耐酸化材料を酸素含有雰囲気に露出する第1露出工程であって、これらの酸素含有雰囲気への露出の間に、第1の表面に沿った第1の半導体島の第1の部分が酸化されるとともに、第3の表面に沿った第2の半導体島の第2の部分が酸化される工程と、
パターン形成された第2の耐酸化層を前記第2の半導体島の上および側面に沿って形成する工程であって、前記第2の耐酸化層は前記第1の半導体島の上および側面には形成されない工程と、
第1の耐酸化層、第2の耐酸化層、第1の半導体島、第2の半導体島、および耐酸化材料を酸素含有雰囲気に露出する第2露出工程であって、これらの酸素含有雰囲気への露出の間に、前記第1の表面に沿った第1の半導体島の第1の部分がさらに酸化されて酸化部分の厚さが拡大する一方、前記第3の表面に沿った第2の半導体島の第2の部分における有意な酸化は生じない工程と
を含み、前記第1の半導体島の前記第2の表面と、前記第2の半導体島の前記第4の表面とは、略同一平面に沿って位置する方法。 - 前記第2露出工程の後で、前記第1の耐酸化層および前記第2の耐酸化層を除去する工程を含む請求項1に記載の方法。
- 前記第2露出工程の後で、前記耐酸化材料を除去する工程を含む請求項2に記載の方法。
- 前記第1の耐酸化層、前記第2の耐酸化層および前記耐酸化材料は窒化物を含む請求項3に記載の方法。
- 前記第1露出工程および前記第2露出工程は、800℃以上の温度で実行される請求項4に記載の方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/375,893 | 2006-03-15 | ||
US11/375,893 US7419866B2 (en) | 2006-03-15 | 2006-03-15 | Process of forming an electronic device including a semiconductor island over an insulating layer |
PCT/US2007/062534 WO2007130728A2 (en) | 2006-03-15 | 2007-02-22 | Electronic device including semiconductor islands of different thicknesses over an insulating layer and a process of forming the same |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2009530828A JP2009530828A (ja) | 2009-08-27 |
JP2009530828A5 JP2009530828A5 (ja) | 2010-03-11 |
JP5366797B2 true JP5366797B2 (ja) | 2013-12-11 |
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ID=38518462
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Application Number | Title | Priority Date | Filing Date |
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JP2009500541A Expired - Fee Related JP5366797B2 (ja) | 2006-03-15 | 2007-02-22 | 絶縁層の上に厚さの異なる複数の半導体島を含む電子デバイスおよびその形成方法 |
Country Status (5)
Country | Link |
---|---|
US (1) | US7419866B2 (ja) |
JP (1) | JP5366797B2 (ja) |
KR (1) | KR20080102388A (ja) |
TW (1) | TWI390736B (ja) |
WO (1) | WO2007130728A2 (ja) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7456055B2 (en) | 2006-03-15 | 2008-11-25 | Freescale Semiconductor, Inc. | Process for forming an electronic device including semiconductor fins |
US8815712B2 (en) * | 2011-12-28 | 2014-08-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for epitaxial re-growth of semiconductor region |
US10366884B1 (en) | 2018-11-08 | 2019-07-30 | Stratio | Methods for forming a germanium island using selective epitaxial growth and a sacrificial filling layer |
Family Cites Families (18)
Publication number | Priority date | Publication date | Assignee | Title |
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JP3017860B2 (ja) * | 1991-10-01 | 2000-03-13 | 株式会社東芝 | 半導体基体およびその製造方法とその半導体基体を用いた半導体装置 |
KR100218299B1 (ko) * | 1996-02-05 | 1999-09-01 | 구본준 | 트랜지스터 제조방법 |
US6870225B2 (en) * | 2001-11-02 | 2005-03-22 | International Business Machines Corporation | Transistor structure with thick recessed source/drain structures and fabrication process of same |
JP2003332580A (ja) * | 2002-05-09 | 2003-11-21 | Matsushita Electric Ind Co Ltd | 半導体装置およびその製造方法 |
US7074623B2 (en) * | 2002-06-07 | 2006-07-11 | Amberwave Systems Corporation | Methods of forming strained-semiconductor-on-insulator finFET device structures |
US6720619B1 (en) * | 2002-12-13 | 2004-04-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor-on-insulator chip incorporating partially-depleted, fully-depleted, and multiple-gate devices |
US6867433B2 (en) * | 2003-04-30 | 2005-03-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor-on-insulator chip incorporating strained-channel partially-depleted, fully-depleted, and multiple-gate transistors |
US6909147B2 (en) * | 2003-05-05 | 2005-06-21 | International Business Machines Corporation | Multi-height FinFETS |
US6927146B2 (en) * | 2003-06-17 | 2005-08-09 | Intel Corporation | Chemical thinning of epitaxial silicon layer over buried oxide |
US6911383B2 (en) * | 2003-06-26 | 2005-06-28 | International Business Machines Corporation | Hybrid planar and finFET CMOS devices |
EP1519421A1 (en) | 2003-09-25 | 2005-03-30 | Interuniversitair Microelektronica Centrum Vzw | Multiple gate semiconductor device and method for forming same |
US7301206B2 (en) * | 2003-08-01 | 2007-11-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor-on-insulator SRAM configured using partially-depleted and fully-depleted transistors |
US7075150B2 (en) * | 2003-12-02 | 2006-07-11 | International Business Machines Corporation | Ultra-thin Si channel MOSFET using a self-aligned oxygen implant and damascene technique |
US7247569B2 (en) * | 2003-12-02 | 2007-07-24 | International Business Machines Corporation | Ultra-thin Si MOSFET device structure and method of manufacture |
JP2005340768A (ja) * | 2004-04-26 | 2005-12-08 | Asahi Glass Co Ltd | 多値不揮発性半導体記憶素子およびその製造方法 |
US20050275018A1 (en) * | 2004-06-10 | 2005-12-15 | Suresh Venkatesan | Semiconductor device with multiple semiconductor layers |
US7211474B2 (en) * | 2005-01-18 | 2007-05-01 | International Business Machines Corporation | SOI device with body contact self-aligned to gate |
US7432149B2 (en) * | 2005-06-23 | 2008-10-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | CMOS on SOI substrates with hybrid crystal orientations |
-
2006
- 2006-03-15 US US11/375,893 patent/US7419866B2/en active Active
-
2007
- 2007-02-22 JP JP2009500541A patent/JP5366797B2/ja not_active Expired - Fee Related
- 2007-02-22 WO PCT/US2007/062534 patent/WO2007130728A2/en active Application Filing
- 2007-02-22 KR KR1020087022446A patent/KR20080102388A/ko not_active Application Discontinuation
- 2007-03-09 TW TW096108232A patent/TWI390736B/zh not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
JP2009530828A (ja) | 2009-08-27 |
TWI390736B (zh) | 2013-03-21 |
WO2007130728A3 (en) | 2008-11-06 |
WO2007130728A2 (en) | 2007-11-15 |
TW200742088A (en) | 2007-11-01 |
KR20080102388A (ko) | 2008-11-25 |
US20070218707A1 (en) | 2007-09-20 |
US7419866B2 (en) | 2008-09-02 |
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