JP5340789B2 - 電子装置及びその製造方法 - Google Patents
電子装置及びその製造方法 Download PDFInfo
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- JP5340789B2 JP5340789B2 JP2009091956A JP2009091956A JP5340789B2 JP 5340789 B2 JP5340789 B2 JP 5340789B2 JP 2009091956 A JP2009091956 A JP 2009091956A JP 2009091956 A JP2009091956 A JP 2009091956A JP 5340789 B2 JP5340789 B2 JP 5340789B2
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- semiconductor device
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15788—Glasses, e.g. amorphous oxides, nitrides or fluorides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2009091956A JP5340789B2 (ja) | 2009-04-06 | 2009-04-06 | 電子装置及びその製造方法 |
| US12/753,170 US8174109B2 (en) | 2009-04-06 | 2010-04-02 | Electronic device and method of manufacturing same |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2009091956A JP5340789B2 (ja) | 2009-04-06 | 2009-04-06 | 電子装置及びその製造方法 |
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| Publication Number | Publication Date |
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| JP2010245259A JP2010245259A (ja) | 2010-10-28 |
| JP2010245259A5 JP2010245259A5 (enExample) | 2012-05-31 |
| JP5340789B2 true JP5340789B2 (ja) | 2013-11-13 |
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| JP2009091956A Active JP5340789B2 (ja) | 2009-04-06 | 2009-04-06 | 電子装置及びその製造方法 |
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| US (1) | US8174109B2 (enExample) |
| JP (1) | JP5340789B2 (enExample) |
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| US8918990B2 (en) * | 2011-06-01 | 2014-12-30 | Lockheed Martin Corporation | Method of forming a solderless printed wiring board |
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| US9691726B2 (en) * | 2014-07-08 | 2017-06-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods for forming fan-out package structure |
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| Publication number | Publication date |
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| JP2010245259A (ja) | 2010-10-28 |
| US8174109B2 (en) | 2012-05-08 |
| US20100252937A1 (en) | 2010-10-07 |
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