JP5340789B2 - 電子装置及びその製造方法 - Google Patents

電子装置及びその製造方法 Download PDF

Info

Publication number
JP5340789B2
JP5340789B2 JP2009091956A JP2009091956A JP5340789B2 JP 5340789 B2 JP5340789 B2 JP 5340789B2 JP 2009091956 A JP2009091956 A JP 2009091956A JP 2009091956 A JP2009091956 A JP 2009091956A JP 5340789 B2 JP5340789 B2 JP 5340789B2
Authority
JP
Japan
Prior art keywords
semiconductor device
electrode
sealing resin
electrode pad
electronic component
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2009091956A
Other languages
English (en)
Japanese (ja)
Other versions
JP2010245259A (ja
JP2010245259A5 (enExample
Inventor
健太 内山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
Original Assignee
Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP2009091956A priority Critical patent/JP5340789B2/ja
Priority to US12/753,170 priority patent/US8174109B2/en
Publication of JP2010245259A publication Critical patent/JP2010245259A/ja
Publication of JP2010245259A5 publication Critical patent/JP2010245259A5/ja
Application granted granted Critical
Publication of JP5340789B2 publication Critical patent/JP5340789B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H10W70/614
    • H10W70/09
    • H10W70/095
    • H10W70/635
    • H10W72/0198
    • H10W74/016
    • H10W74/114
    • H10W74/117
    • H10W90/00
    • H10W70/093
    • H10W70/099
    • H10W72/073
    • H10W72/552
    • H10W72/874
    • H10W72/9413
    • H10W74/00
    • H10W74/019
    • H10W74/142
    • H10W74/15
    • H10W90/10
    • H10W90/20
    • H10W90/724
    • H10W90/734
    • H10W90/754

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
JP2009091956A 2009-04-06 2009-04-06 電子装置及びその製造方法 Active JP5340789B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2009091956A JP5340789B2 (ja) 2009-04-06 2009-04-06 電子装置及びその製造方法
US12/753,170 US8174109B2 (en) 2009-04-06 2010-04-02 Electronic device and method of manufacturing same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2009091956A JP5340789B2 (ja) 2009-04-06 2009-04-06 電子装置及びその製造方法

Publications (3)

Publication Number Publication Date
JP2010245259A JP2010245259A (ja) 2010-10-28
JP2010245259A5 JP2010245259A5 (enExample) 2012-05-31
JP5340789B2 true JP5340789B2 (ja) 2013-11-13

Family

ID=42825499

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009091956A Active JP5340789B2 (ja) 2009-04-06 2009-04-06 電子装置及びその製造方法

Country Status (2)

Country Link
US (1) US8174109B2 (enExample)
JP (1) JP5340789B2 (enExample)

Families Citing this family (36)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5372579B2 (ja) * 2009-04-10 2013-12-18 新光電気工業株式会社 半導体装置及びその製造方法、並びに電子装置
JP5330065B2 (ja) 2009-04-13 2013-10-30 新光電気工業株式会社 電子装置及びその製造方法
JP5732839B2 (ja) * 2010-12-13 2015-06-10 住友ベークライト株式会社 半導体素子封止体の製造方法および半導体パッケージの製造方法
JP5732838B2 (ja) * 2010-12-13 2015-06-10 住友ベークライト株式会社 半導体素子封止体の製造方法および半導体パッケージの製造方法
US8338294B2 (en) 2011-03-31 2012-12-25 Soitec Methods of forming bonded semiconductor structures including two or more processed semiconductor structures carried by a common substrate, and semiconductor structures formed by such methods
US20120248621A1 (en) * 2011-03-31 2012-10-04 S.O.I.Tec Silicon On Insulator Technologies Methods of forming bonded semiconductor structures, and semiconductor structures formed by such methods
US8918990B2 (en) * 2011-06-01 2014-12-30 Lockheed Martin Corporation Method of forming a solderless printed wiring board
JP2013069807A (ja) * 2011-09-21 2013-04-18 Shinko Electric Ind Co Ltd 半導体パッケージ及びその製造方法
US9123763B2 (en) 2011-10-12 2015-09-01 Taiwan Semiconductor Manufacturing Company, Ltd. Package-on-package (PoP) structure having at least one package comprising one die being disposed in a core material between first and second surfaces of the core material
US8975741B2 (en) 2011-10-17 2015-03-10 Taiwan Semiconductor Manufacturing Company, Ltd. Process for forming package-on-package structures
JP5780228B2 (ja) * 2011-11-11 2015-09-16 住友ベークライト株式会社 半導体装置の製造方法
US8623711B2 (en) * 2011-12-15 2014-01-07 Stats Chippac Ltd. Integrated circuit packaging system with package-on-package and method of manufacture thereof
US9219029B2 (en) 2011-12-15 2015-12-22 Stats Chippac Ltd. Integrated circuit packaging system with terminals and method of manufacture thereof
US8629567B2 (en) 2011-12-15 2014-01-14 Stats Chippac Ltd. Integrated circuit packaging system with contacts and method of manufacture thereof
KR101947722B1 (ko) * 2012-06-07 2019-04-25 삼성전자주식회사 적층 반도체 패키지 및 이의 제조방법
US8866287B2 (en) * 2012-09-29 2014-10-21 Intel Corporation Embedded structures for package-on-package architecture
CN104051411B (zh) 2013-03-15 2018-08-28 台湾积体电路制造股份有限公司 叠层封装结构
US9768048B2 (en) * 2013-03-15 2017-09-19 Taiwan Semiconductor Manufacturing Company, Ltd. Package on-package structure
KR101999114B1 (ko) * 2013-06-03 2019-07-11 에스케이하이닉스 주식회사 반도체 패키지
US9711485B1 (en) * 2014-02-04 2017-07-18 Amkor Technology, Inc. Thin bonded interposer package
JP2015195263A (ja) * 2014-03-31 2015-11-05 マイクロン テクノロジー, インク. 半導体装置及びその製造方法
US9236355B2 (en) * 2014-04-17 2016-01-12 Apple Inc. EMI shielded wafer level fan-out pop package
US9859265B2 (en) * 2014-06-06 2018-01-02 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and methods of forming the same
FR3022690B1 (fr) * 2014-06-24 2016-07-22 Commissariat Energie Atomique Dispositif de connexion electrique comportant des elements de connexion a position commandable
US10257937B2 (en) * 2014-07-07 2019-04-09 Infineon Technologies Austria Ag Device for electrically coupling a plurality of semiconductor device layers by a common conductive layer
US9691726B2 (en) * 2014-07-08 2017-06-27 Taiwan Semiconductor Manufacturing Company, Ltd. Methods for forming fan-out package structure
US9601464B2 (en) 2014-07-10 2017-03-21 Apple Inc. Thermally enhanced package-on-package structure
US10109593B2 (en) 2015-07-23 2018-10-23 Apple Inc. Self shielded system in package (SiP) modules
US20170098589A1 (en) * 2015-10-05 2017-04-06 Mediatek Inc. Fan-out wafer level package structure
US9721903B2 (en) 2015-12-21 2017-08-01 Apple Inc. Vertical interconnects for self shielded system in package (SiP) modules
JP6713289B2 (ja) * 2016-01-28 2020-06-24 新光電気工業株式会社 半導体装置及び半導体装置の製造方法
JP2018018936A (ja) * 2016-07-27 2018-02-01 イビデン株式会社 配線基板
US10784220B2 (en) * 2017-03-30 2020-09-22 Taiwan Semiconductor Manufacturing Co., Ltd. Plurality of semiconductor devices encapsulated by a molding material attached to a redistribution layer
US10074604B1 (en) * 2017-04-28 2018-09-11 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out package and method of fabricating the same
KR101892869B1 (ko) * 2017-10-20 2018-08-28 삼성전기주식회사 팬-아웃 반도체 패키지
JPWO2024029138A1 (enExample) * 2022-08-01 2024-02-08

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03155183A (ja) * 1989-11-14 1991-07-03 Seiko Instr Inc 積層プリント基板
US5241456A (en) * 1990-07-02 1993-08-31 General Electric Company Compact high density interconnect structure
US5111278A (en) * 1991-03-27 1992-05-05 Eichelberger Charles W Three-dimensional multichip module systems
US5222014A (en) * 1992-03-02 1993-06-22 Motorola, Inc. Three-dimensional multi-chip pad array carrier
US5353498A (en) * 1993-02-08 1994-10-11 General Electric Company Method for fabricating an integrated circuit module
JPH08167630A (ja) * 1994-12-15 1996-06-25 Hitachi Ltd チップ接続構造
US6538210B2 (en) * 1999-12-20 2003-03-25 Matsushita Electric Industrial Co., Ltd. Circuit component built-in module, radio device having the same, and method for producing the same
US6734534B1 (en) 2000-08-16 2004-05-11 Intel Corporation Microelectronic substrate with integrated devices
AU2000269991A1 (en) 2000-08-24 2002-03-04 Jean-Pierre Abgottspon Hydrophobic rheologically effective products, method for production and use thereof
JP3739699B2 (ja) * 2001-12-20 2006-01-25 松下電器産業株式会社 電子部品実装済み部品の製造方法及び製造装置
JP3853219B2 (ja) * 2002-01-18 2006-12-06 イビデン株式会社 半導体素子内蔵基板および多層回路基板
JP3918681B2 (ja) * 2002-08-09 2007-05-23 カシオ計算機株式会社 半導体装置
JP4145301B2 (ja) * 2003-01-15 2008-09-03 富士通株式会社 半導体装置及び三次元実装半導体装置
JP2005317903A (ja) * 2004-03-31 2005-11-10 Alps Electric Co Ltd 回路部品モジュール、回路部品モジュールスタック、記録媒体およびこれらの製造方法
JP2006165175A (ja) * 2004-12-06 2006-06-22 Alps Electric Co Ltd 回路部品モジュールおよび電子回路装置並びに回路部品モジュールの製造方法
JP4433298B2 (ja) * 2004-12-16 2010-03-17 パナソニック株式会社 多段構成半導体モジュール
JP4504798B2 (ja) * 2004-12-16 2010-07-14 パナソニック株式会社 多段構成半導体モジュール
JP4507101B2 (ja) * 2005-06-30 2010-07-21 エルピーダメモリ株式会社 半導体記憶装置及びその製造方法

Also Published As

Publication number Publication date
US20100252937A1 (en) 2010-10-07
JP2010245259A (ja) 2010-10-28
US8174109B2 (en) 2012-05-08

Similar Documents

Publication Publication Date Title
JP5340789B2 (ja) 電子装置及びその製造方法
JP5330065B2 (ja) 電子装置及びその製造方法
JP5535494B2 (ja) 半導体装置
JP5193898B2 (ja) 半導体装置及び電子装置
JP5188426B2 (ja) 半導体装置及びその製造方法、電子装置
JP5372579B2 (ja) 半導体装置及びその製造方法、並びに電子装置
TW201935582A (zh) 半導體封裝及其製造方法
CN110299329A (zh) 一种封装结构及其制作方法、电子设备
JP5147755B2 (ja) 半導体装置及びその製造方法
JP2011187800A (ja) 半導体装置及びその製造方法
JP2010232333A (ja) 半導体装置及びその製造方法、並びに電子装置
JP5357239B2 (ja) 配線基板、半導体装置、及び配線基板の製造方法
KR20140029268A (ko) 반도체 장치의 제조 방법
TW202131472A (zh) 半導體裝置以及其製造方法
JP7269755B2 (ja) 電子装置および電子装置の製造方法
JP7265877B2 (ja) 配線基板
JP2018046218A (ja) リードフレーム及びその製造方法と電子部品装置
JP5693763B2 (ja) 半導体装置及びその製造方法
JP4955259B2 (ja) 配線基板、半導体装置、及び配線基板の製造方法
JP2008135553A (ja) 基板積層方法及び基板が積層された半導体装置
JP2017191874A (ja) 配線基板及びその製造方法
US20250316567A1 (en) Mounting substrate and mounting substrate manufacturing method
JP2025057775A (ja) 配線基板及びその製造方法、半導体装置
CN113838829A (zh) 封装载板及其制作方法
CN106856176A (zh) 半导体封装结构及其制作方法

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20120405

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20120405

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20121012

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20121023

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20121221

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20130730

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20130807

R150 Certificate of patent or registration of utility model

Ref document number: 5340789

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

Free format text: JAPANESE INTERMEDIATE CODE: R150