JP5330065B2 - 電子装置及びその製造方法 - Google Patents

電子装置及びその製造方法 Download PDF

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Publication number
JP5330065B2
JP5330065B2 JP2009096741A JP2009096741A JP5330065B2 JP 5330065 B2 JP5330065 B2 JP 5330065B2 JP 2009096741 A JP2009096741 A JP 2009096741A JP 2009096741 A JP2009096741 A JP 2009096741A JP 5330065 B2 JP5330065 B2 JP 5330065B2
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Prior art keywords
semiconductor device
electrode
insulating member
electrode pad
electronic component
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JP2009096741A
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English (en)
Japanese (ja)
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JP2010251395A (ja
JP2010251395A5 (https=
Inventor
健太 内山
昭彦 立岩
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Shinko Electric Industries Co Ltd
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Shinko Electric Industries Co Ltd
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Priority to JP2009096741A priority Critical patent/JP5330065B2/ja
Priority to US12/755,515 priority patent/US8786103B2/en
Publication of JP2010251395A publication Critical patent/JP2010251395A/ja
Publication of JP2010251395A5 publication Critical patent/JP2010251395A5/ja
Application granted granted Critical
Publication of JP5330065B2 publication Critical patent/JP5330065B2/ja
Priority to US14/305,229 priority patent/US9515050B2/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/093—Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H10W70/614—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together the multiple chips being integrally enclosed
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H10W70/635—Through-vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/0198—Manufacture or treatment batch processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/401—Package configurations characterised by multiple insulating or insulated package substrates, interposers or RDLs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/9413—Dispositions of bond pads on encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/131—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed
    • H10W74/142—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed the encapsulations exposing the passive side of the semiconductor body
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/10—Configurations of laterally-adjacent chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/297—Configurations of stacked chips characterised by the through-semiconductor vias [TSVs] in the stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP2009096741A 2009-04-13 2009-04-13 電子装置及びその製造方法 Active JP5330065B2 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2009096741A JP5330065B2 (ja) 2009-04-13 2009-04-13 電子装置及びその製造方法
US12/755,515 US8786103B2 (en) 2009-04-13 2010-04-07 Stacked chips package having feed-through electrode connecting the first and second semiconductor components via an adhesive layer
US14/305,229 US9515050B2 (en) 2009-04-13 2014-06-16 Electronic apparatus having a resin filled through electrode configured to go through first and second semiconductor components

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2009096741A JP5330065B2 (ja) 2009-04-13 2009-04-13 電子装置及びその製造方法

Publications (3)

Publication Number Publication Date
JP2010251395A JP2010251395A (ja) 2010-11-04
JP2010251395A5 JP2010251395A5 (https=) 2012-05-31
JP5330065B2 true JP5330065B2 (ja) 2013-10-30

Family

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JP2009096741A Active JP5330065B2 (ja) 2009-04-13 2009-04-13 電子装置及びその製造方法

Country Status (2)

Country Link
US (2) US8786103B2 (https=)
JP (1) JP5330065B2 (https=)

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JP2010205921A (ja) * 2009-03-03 2010-09-16 Olympus Corp 半導体装置および半導体装置の製造方法
US10672748B1 (en) * 2010-06-02 2020-06-02 Maxim Integrated Products, Inc. Use of device assembly for a generalization of three-dimensional heterogeneous technologies integration
US8546193B2 (en) * 2010-11-02 2013-10-01 Stats Chippac, Ltd. Semiconductor device and method of forming penetrable film encapsulant around semiconductor die and interconnect structure
US20130154106A1 (en) * 2011-12-14 2013-06-20 Broadcom Corporation Stacked Packaging Using Reconstituted Wafers
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CN104412372B (zh) * 2012-06-29 2018-01-26 索尼公司 半导体装置、半导体装置的制造方法和电子设备
JP6320681B2 (ja) * 2013-03-29 2018-05-09 ローム株式会社 半導体装置
US9147663B2 (en) 2013-05-28 2015-09-29 Intel Corporation Bridge interconnection with layered interconnect structures
US9209154B2 (en) 2013-12-04 2015-12-08 Bridge Semiconductor Corporation Semiconductor package with package-on-package stacking capability and method of manufacturing the same
US9184128B2 (en) * 2013-12-13 2015-11-10 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC package and methods of forming the same
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US9373604B2 (en) * 2014-08-20 2016-06-21 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structures for wafer level package and methods of forming same
US9659896B2 (en) 2014-08-20 2017-05-23 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structures for wafer level package and methods of forming same
US9484285B2 (en) 2014-08-20 2016-11-01 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structures for wafer level package and methods of forming same
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US9786631B2 (en) 2014-11-26 2017-10-10 Taiwan Semiconductor Manufacturing Company, Ltd. Device package with reduced thickness and method for forming same
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JP2016201414A (ja) * 2015-04-08 2016-12-01 日立化成株式会社 半導体装置及びその製造方法
JP6625491B2 (ja) * 2016-06-29 2019-12-25 新光電気工業株式会社 配線基板、半導体装置、配線基板の製造方法
US20180130761A1 (en) * 2016-11-09 2018-05-10 Samsung Electro-Mechanics Co., Ltd. Semiconductor package, manufacturing method thereof, and electronic element module using the same
US10784220B2 (en) * 2017-03-30 2020-09-22 Taiwan Semiconductor Manufacturing Co., Ltd. Plurality of semiconductor devices encapsulated by a molding material attached to a redistribution layer
US10181449B1 (en) * 2017-09-28 2019-01-15 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structure
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Also Published As

Publication number Publication date
US8786103B2 (en) 2014-07-22
US20140291865A1 (en) 2014-10-02
JP2010251395A (ja) 2010-11-04
US20100258944A1 (en) 2010-10-14
US9515050B2 (en) 2016-12-06

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