JP5313854B2 - 配線基板及び半導体装置 - Google Patents

配線基板及び半導体装置 Download PDF

Info

Publication number
JP5313854B2
JP5313854B2 JP2009287132A JP2009287132A JP5313854B2 JP 5313854 B2 JP5313854 B2 JP 5313854B2 JP 2009287132 A JP2009287132 A JP 2009287132A JP 2009287132 A JP2009287132 A JP 2009287132A JP 5313854 B2 JP5313854 B2 JP 5313854B2
Authority
JP
Japan
Prior art keywords
wiring
connection pad
layer
receiving electrode
wiring layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2009287132A
Other languages
English (en)
Japanese (ja)
Other versions
JP2011129729A (ja
JP2011129729A5 (enExample
Inventor
啓 村山
昌宏 春原
晶紀 白石
秀明 坂口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
Original Assignee
Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP2009287132A priority Critical patent/JP5313854B2/ja
Priority to US12/958,730 priority patent/US8350390B2/en
Publication of JP2011129729A publication Critical patent/JP2011129729A/ja
Publication of JP2011129729A5 publication Critical patent/JP2011129729A5/ja
Application granted granted Critical
Publication of JP5313854B2 publication Critical patent/JP5313854B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/115—Via connections; Lands around holes or via connections
    • H05K1/116—Lands, clearance holes or other lay-out details concerning the surrounding of a via
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
    • H05K1/113—Via provided in pad; Pad over filled via
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H10W70/635—Through-vias
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09672—Superposed layout, i.e. in different planes
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/0979—Redundant conductors or connections, i.e. more than one current path between two points
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10674—Flip chip
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
    • H05K3/4605—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated made from inorganic insulating material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP2009287132A 2009-12-18 2009-12-18 配線基板及び半導体装置 Active JP5313854B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2009287132A JP5313854B2 (ja) 2009-12-18 2009-12-18 配線基板及び半導体装置
US12/958,730 US8350390B2 (en) 2009-12-18 2010-12-02 Wiring substrate and semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2009287132A JP5313854B2 (ja) 2009-12-18 2009-12-18 配線基板及び半導体装置

Publications (3)

Publication Number Publication Date
JP2011129729A JP2011129729A (ja) 2011-06-30
JP2011129729A5 JP2011129729A5 (enExample) 2012-10-18
JP5313854B2 true JP5313854B2 (ja) 2013-10-09

Family

ID=44149923

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009287132A Active JP5313854B2 (ja) 2009-12-18 2009-12-18 配線基板及び半導体装置

Country Status (2)

Country Link
US (1) US8350390B2 (enExample)
JP (1) JP5313854B2 (enExample)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2592915B1 (en) * 2010-07-06 2022-01-26 Fujikura, Ltd. Manufacturing method for laminated wiring board
CN103608915B (zh) * 2011-06-21 2016-09-07 株式会社村田制作所 电路模块
US8952540B2 (en) * 2011-06-30 2015-02-10 Intel Corporation In situ-built pin-grid arrays for coreless substrates, and methods of making same
US9275925B2 (en) 2013-03-12 2016-03-01 Taiwan Semiconductor Manufacturing Company, Ltd. System and method for an improved interconnect structure
JP2015173144A (ja) * 2014-03-11 2015-10-01 株式会社東芝 配線基板とそれを用いた半導体装置
TWI554174B (zh) * 2014-11-04 2016-10-11 上海兆芯集成電路有限公司 線路基板和半導體封裝結構
JP2020013917A (ja) * 2018-07-19 2020-01-23 京セラ株式会社 配線基板
WO2021140855A1 (ja) * 2020-01-10 2021-07-15 住友電気工業株式会社 フレキシブルプリント配線板及びその製造方法

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW430935B (en) * 1999-03-19 2001-04-21 Ind Tech Res Inst Frame type bonding pad structure having a low parasitic capacitance
JP4248761B2 (ja) * 2001-04-27 2009-04-02 新光電気工業株式会社 半導体パッケージ及びその製造方法並びに半導体装置
US6844631B2 (en) * 2002-03-13 2005-01-18 Freescale Semiconductor, Inc. Semiconductor device having a bond pad and method therefor
JP2003289104A (ja) * 2002-03-28 2003-10-10 Ricoh Co Ltd 半導体装置の保護回路及び半導体装置
JP3639265B2 (ja) * 2002-05-28 2005-04-20 松下電器産業株式会社 半導体装置及びその製造方法
US7138185B2 (en) * 2002-07-05 2006-11-21 Fuji Photo Film Co., Ltd. Anti-reflection film, polarizing plate and display device
JP2005101248A (ja) * 2003-09-25 2005-04-14 Seiko Epson Corp 半導体装置及びその製造方法、回路基板並びに電子機器
JP2006190771A (ja) * 2005-01-05 2006-07-20 Renesas Technology Corp 半導体装置
JP4671814B2 (ja) * 2005-09-02 2011-04-20 パナソニック株式会社 半導体装置
JP2007087975A (ja) * 2005-09-16 2007-04-05 Ricoh Co Ltd 半導体装置
JP2008112765A (ja) 2006-10-30 2008-05-15 Matsushita Electric Ind Co Ltd 半導体装置

Also Published As

Publication number Publication date
JP2011129729A (ja) 2011-06-30
US8350390B2 (en) 2013-01-08
US20110147951A1 (en) 2011-06-23

Similar Documents

Publication Publication Date Title
JP6325605B2 (ja) 電子部品内蔵基板
JP4581768B2 (ja) 半導体装置の製造方法
JP4387231B2 (ja) キャパシタ実装配線基板及びその製造方法
US9177899B2 (en) Semiconductor package and method for fabricating base for semiconductor package
JP2011129729A (ja) 配線基板及び半導体装置
US20180102338A1 (en) Circuit board with bridge chiplets
JP5363384B2 (ja) 配線基板及びその製造方法
JP6316609B2 (ja) 配線基板及び半導体装置と配線基板の製造方法及び半導体装置の製造方法
KR20120104387A (ko) 비아 트레이스 연결을 갖는 회로 보드 및 그 제조 방법
JP5547615B2 (ja) 配線基板、半導体装置及び配線基板の製造方法
US9301394B2 (en) Manufacturing method and electronic module with new routing possibilities
JP2002329802A (ja) 半導体パッケージ及びその製造方法並びに半導体装置
TW201132265A (en) Circuit board with offset via
JP6570924B2 (ja) 電子部品装置及びその製造方法
JP4829998B2 (ja) キャパシタ実装配線基板
KR102826729B1 (ko) 반도체 장치 및 이의 제조 방법
CN104869747A (zh) 印刷布线板和印刷布线板的制造方法
JP2010206021A (ja) 電子部品実装構造体、およびその製造方法
JP2005011883A (ja) 配線基板、半導体装置および配線基板の製造方法
KR20120028008A (ko) 전자부품 내장형 인쇄회로기판 및 이의 제조 방법
JP5363377B2 (ja) 配線基板及びその製造方法
CN102017137A (zh) 高速存储器封装
JP2004228446A (ja) プリント基板
KR101001638B1 (ko) 반도체 패키지
JP2019114678A (ja) プリント配線板の製造方法

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20120903

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20120903

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20130613

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20130625

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20130704

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

Ref document number: 5313854

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150