JP2011129729A - 配線基板及び半導体装置 - Google Patents
配線基板及び半導体装置 Download PDFInfo
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- JP2011129729A JP2011129729A JP2009287132A JP2009287132A JP2011129729A JP 2011129729 A JP2011129729 A JP 2011129729A JP 2009287132 A JP2009287132 A JP 2009287132A JP 2009287132 A JP2009287132 A JP 2009287132A JP 2011129729 A JP2011129729 A JP 2011129729A
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/115—Via connections; Lands around holes or via connections
- H05K1/116—Lands, clearance holes or other lay-out details concerning the surrounding of a via
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
- H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
- H05K1/113—Via provided in pad; Pad over filled via
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
- H05K2201/09672—Superposed layout, i.e. in different planes
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
- H05K2201/0979—Redundant conductors or connections, i.e. more than one current path between two points
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10674—Flip chip
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
- H05K3/4605—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated made from inorganic insulating material
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
【解決手段】配線層22と、配線層22の上に形成された絶縁層32と、絶縁層32の上に形成された接続パッドCと、絶縁層32を貫通して形成され、配線層22と接続パッドCとを接続するビア導体VC2とを含み、接続パッドCの1層下の配線層22は、接続パッドCに対応する領域に、接続パッドCより小さい面積のビア受け用電極部22a,22c(22x)と、それと分離された配線部22b(22y)とを備えて形成され、ビア受け用電極部22a,22c(22x)がビア導体VC2を介して接続パッドCに接続されている。
【選択図】図2
Description
配線基板では、各接続パッドの下にその主要部に接続される一つのビア導体が配置され、接続パッドと同等面積で配置された下側配線層のビアパッドの上にビア導体が配置されて層間接続される。
本発明の実施形態を説明する前に、本発明に関連する関連技術について説明する。図1は関連技術の配線基板を示す断面図である。
図2は本発明の実施形態の配線基板を示す断面図及び部分透視平面図である。
Claims (8)
- 配線層と、
前記配線層の上に形成された絶縁層と、
前記絶縁層の上に形成された接続パッドと、
前記絶縁層を貫通して形成され、前記配線層と前記接続パッドとを接続するビア導体とを有し、
前記接続パッドの1層下の前記配線層は、
前記接続パッドに対応する領域に、前記接続パッドより小さい面積のビア受け用電極部と、前記ビア受け用電極部と分離された配線部とを備えて形成され、
前記ビア受け用電極部が前記ビア導体を介して前記接続パッドに接続されていることを特徴とする配線基板。 - 前記ビア受け用電極部は、前記接続パッドに対応する領域の両端側に分離されて配置され、前記配線部は前記ビア受け用電極部の間に配置されていることを特徴とする請求項1に記載の配線基板。
- 前記ビア受け用電極部は、前記接続パッドに対応する領域の両端側に配置され、前記接続パッドに対応する領域から外側に延在し、かつ前記絶縁層上で繋がっており、
前記配線部は前記ビア受け用電極部の間に配置されていることを特徴とする請求項1に記載の配線基板。 - 前記ビア導体は、前記ビア受け用電極部の上に複数個で相互に分離されて配置されていることを特徴とする請求項1に記載の配線基板。
- 前記接続パッドの1層下の前記配線層は、前記接続パッドと同一層からなる他の接続パッドに対応する領域に、前記他の接続パッドに対応する大きさのビアパッドを備えて形成されており、
前記ビアパッドは、前記ビア受け用電極部上の前記ビア導体と同一径の複数のビア導体を介して前記他の接続パッドに接続されていることを特徴とする請求項1に記載の配線基板。 - 前記配線層はシリコン基板の片面又は両面にn層(nは1以上の整数)で形成されてことを特徴とする請求項1乃至5のいずれか一項に記載の配線基板。
- 前記接続パッドは、前記配線層の厚みより高いバンプ電極として形成されていることを特徴とする請求項1乃至5のいずれか一項に記載の配線基板。
- 請求項1乃至7のいずれか一項の配線基板と、
前記配線基板の前記接続パッドにフリップチップ接続された半導体チップとを有することを特徴とする半導体装置。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
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JP2009287132A JP5313854B2 (ja) | 2009-12-18 | 2009-12-18 | 配線基板及び半導体装置 |
US12/958,730 US8350390B2 (en) | 2009-12-18 | 2010-12-02 | Wiring substrate and semiconductor device |
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JP2009287132A JP5313854B2 (ja) | 2009-12-18 | 2009-12-18 | 配線基板及び半導体装置 |
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JP2011129729A true JP2011129729A (ja) | 2011-06-30 |
JP2011129729A5 JP2011129729A5 (ja) | 2012-10-18 |
JP5313854B2 JP5313854B2 (ja) | 2013-10-09 |
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Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5411362B2 (ja) * | 2010-07-06 | 2014-02-12 | 株式会社フジクラ | 積層配線基板及びその製造方法 |
JP2020013917A (ja) * | 2018-07-19 | 2020-01-23 | 京セラ株式会社 | 配線基板 |
CN114365587A (zh) * | 2020-01-10 | 2022-04-15 | 住友电气工业株式会社 | 柔性印刷布线板及其制造方法 |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
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WO2012176402A1 (ja) * | 2011-06-21 | 2012-12-27 | 株式会社村田製作所 | 回路モジュール |
US8952540B2 (en) * | 2011-06-30 | 2015-02-10 | Intel Corporation | In situ-built pin-grid arrays for coreless substrates, and methods of making same |
US9275925B2 (en) | 2013-03-12 | 2016-03-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | System and method for an improved interconnect structure |
JP2015173144A (ja) * | 2014-03-11 | 2015-10-01 | 株式会社東芝 | 配線基板とそれを用いた半導体装置 |
TWI554174B (zh) * | 2014-11-04 | 2016-10-11 | 上海兆芯集成電路有限公司 | 線路基板和半導體封裝結構 |
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JP2002329802A (ja) * | 2001-04-27 | 2002-11-15 | Shinko Electric Ind Co Ltd | 半導体パッケージ及びその製造方法並びに半導体装置 |
JP2003347472A (ja) * | 2002-05-28 | 2003-12-05 | Matsushita Electric Ind Co Ltd | 半導体装置及びその製造方法 |
JP2005101248A (ja) * | 2003-09-25 | 2005-04-14 | Seiko Epson Corp | 半導体装置及びその製造方法、回路基板並びに電子機器 |
JP2006190771A (ja) * | 2005-01-05 | 2006-07-20 | Renesas Technology Corp | 半導体装置 |
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TW430935B (en) * | 1999-03-19 | 2001-04-21 | Ind Tech Res Inst | Frame type bonding pad structure having a low parasitic capacitance |
US6844631B2 (en) * | 2002-03-13 | 2005-01-18 | Freescale Semiconductor, Inc. | Semiconductor device having a bond pad and method therefor |
JP2003289104A (ja) * | 2002-03-28 | 2003-10-10 | Ricoh Co Ltd | 半導体装置の保護回路及び半導体装置 |
US7138185B2 (en) * | 2002-07-05 | 2006-11-21 | Fuji Photo Film Co., Ltd. | Anti-reflection film, polarizing plate and display device |
JP4671814B2 (ja) * | 2005-09-02 | 2011-04-20 | パナソニック株式会社 | 半導体装置 |
JP2007087975A (ja) * | 2005-09-16 | 2007-04-05 | Ricoh Co Ltd | 半導体装置 |
JP2008112765A (ja) | 2006-10-30 | 2008-05-15 | Matsushita Electric Ind Co Ltd | 半導体装置 |
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- 2009-12-18 JP JP2009287132A patent/JP5313854B2/ja active Active
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- 2010-12-02 US US12/958,730 patent/US8350390B2/en active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2002329802A (ja) * | 2001-04-27 | 2002-11-15 | Shinko Electric Ind Co Ltd | 半導体パッケージ及びその製造方法並びに半導体装置 |
JP2003347472A (ja) * | 2002-05-28 | 2003-12-05 | Matsushita Electric Ind Co Ltd | 半導体装置及びその製造方法 |
JP2005101248A (ja) * | 2003-09-25 | 2005-04-14 | Seiko Epson Corp | 半導体装置及びその製造方法、回路基板並びに電子機器 |
JP2006190771A (ja) * | 2005-01-05 | 2006-07-20 | Renesas Technology Corp | 半導体装置 |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5411362B2 (ja) * | 2010-07-06 | 2014-02-12 | 株式会社フジクラ | 積層配線基板及びその製造方法 |
JP2020013917A (ja) * | 2018-07-19 | 2020-01-23 | 京セラ株式会社 | 配線基板 |
CN114365587A (zh) * | 2020-01-10 | 2022-04-15 | 住友电气工业株式会社 | 柔性印刷布线板及其制造方法 |
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US20110147951A1 (en) | 2011-06-23 |
US8350390B2 (en) | 2013-01-08 |
JP5313854B2 (ja) | 2013-10-09 |
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