JP5311609B2 - シリコンインターポーザの製造方法およびシリコンインターポーザと、これを用いた半導体装置用パッケージおよび半導体装置 - Google Patents

シリコンインターポーザの製造方法およびシリコンインターポーザと、これを用いた半導体装置用パッケージおよび半導体装置 Download PDF

Info

Publication number
JP5311609B2
JP5311609B2 JP2007281345A JP2007281345A JP5311609B2 JP 5311609 B2 JP5311609 B2 JP 5311609B2 JP 2007281345 A JP2007281345 A JP 2007281345A JP 2007281345 A JP2007281345 A JP 2007281345A JP 5311609 B2 JP5311609 B2 JP 5311609B2
Authority
JP
Japan
Prior art keywords
electrode
thermal expansion
silicon
hole
silicon wafer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2007281345A
Other languages
English (en)
Japanese (ja)
Other versions
JP2009111120A5 (enExample
JP2009111120A (ja
Inventor
昌宏 春原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
Original Assignee
Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP2007281345A priority Critical patent/JP5311609B2/ja
Priority to KR1020080103373A priority patent/KR20090045012A/ko
Priority to US12/259,564 priority patent/US7851359B2/en
Priority to EP08167981A priority patent/EP2056343A3/en
Publication of JP2009111120A publication Critical patent/JP2009111120A/ja
Publication of JP2009111120A5 publication Critical patent/JP2009111120A5/ja
Application granted granted Critical
Publication of JP5311609B2 publication Critical patent/JP5311609B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/147—Semiconductor insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electroplating Methods And Accessories (AREA)
JP2007281345A 2007-10-30 2007-10-30 シリコンインターポーザの製造方法およびシリコンインターポーザと、これを用いた半導体装置用パッケージおよび半導体装置 Active JP5311609B2 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2007281345A JP5311609B2 (ja) 2007-10-30 2007-10-30 シリコンインターポーザの製造方法およびシリコンインターポーザと、これを用いた半導体装置用パッケージおよび半導体装置
KR1020080103373A KR20090045012A (ko) 2007-10-30 2008-10-22 실리콘 인터포저 제조 방법, 실리콘 인터포저 및 실리콘 인터포저를 구비하는 반도체 장치 패키지 및 반도체 장치
US12/259,564 US7851359B2 (en) 2007-10-30 2008-10-28 Silicon interposer producing method, silicon interposer and semiconductor device package and semiconductor device incorporating silicon interposer
EP08167981A EP2056343A3 (en) 2007-10-30 2008-10-30 Silicon interposer producing method, silicon interposer and seminconductor device package and semiconductor device incorporating silicon interposer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2007281345A JP5311609B2 (ja) 2007-10-30 2007-10-30 シリコンインターポーザの製造方法およびシリコンインターポーザと、これを用いた半導体装置用パッケージおよび半導体装置

Publications (3)

Publication Number Publication Date
JP2009111120A JP2009111120A (ja) 2009-05-21
JP2009111120A5 JP2009111120A5 (enExample) 2010-09-16
JP5311609B2 true JP5311609B2 (ja) 2013-10-09

Family

ID=40377454

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007281345A Active JP5311609B2 (ja) 2007-10-30 2007-10-30 シリコンインターポーザの製造方法およびシリコンインターポーザと、これを用いた半導体装置用パッケージおよび半導体装置

Country Status (4)

Country Link
US (1) US7851359B2 (enExample)
EP (1) EP2056343A3 (enExample)
JP (1) JP5311609B2 (enExample)
KR (1) KR20090045012A (enExample)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4833307B2 (ja) * 2009-02-24 2011-12-07 インターナショナル・ビジネス・マシーンズ・コーポレーション 半導体モジュール、端子板、端子板の製造方法および半導体モジュールの製造方法
JP5532744B2 (ja) 2009-08-20 2014-06-25 富士通株式会社 マルチチップモジュール及びマルチチップモジュールの製造方法
KR101060862B1 (ko) 2009-09-14 2011-08-31 삼성전기주식회사 인터포저 및 그의 제조방법
JP5367523B2 (ja) * 2009-09-25 2013-12-11 新光電気工業株式会社 配線基板及び配線基板の製造方法
US20110089531A1 (en) * 2009-10-16 2011-04-21 Teledyne Scientific & Imaging, Llc Interposer Based Monolithic Microwave Integrate Circuit (iMMIC)
KR101678539B1 (ko) * 2010-07-21 2016-11-23 삼성전자 주식회사 적층 패키지, 반도체 패키지 및 적층 패키지의 제조 방법
US8723049B2 (en) * 2011-06-09 2014-05-13 Tessera, Inc. Low-stress TSV design using conductive particles
CN106783787B (zh) * 2017-01-24 2025-04-04 深圳市槟城电子股份有限公司 用于芯片封装的电极以及使用该电极的芯片封装结构
CN116710220A (zh) * 2021-01-28 2023-09-05 京瓷株式会社 布线基板

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5266181A (en) * 1991-11-27 1993-11-30 C. Uyemura & Co., Ltd. Controlled composite deposition method
US5614043A (en) 1992-09-17 1997-03-25 Coors Ceramics Company Method for fabricating electronic components incorporating ceramic-metal composites
JPH0790413A (ja) * 1993-09-22 1995-04-04 Sumitomo Special Metals Co Ltd 複合材料
US6193910B1 (en) * 1997-11-11 2001-02-27 Ngk Spark Plug Co., Ltd. Paste for through-hole filling and printed wiring board using the same
JP4246132B2 (ja) * 2004-10-04 2009-04-02 シャープ株式会社 半導体装置およびその製造方法
JP4698296B2 (ja) * 2005-06-17 2011-06-08 新光電気工業株式会社 貫通電極を有する半導体装置の製造方法
JP2007027451A (ja) 2005-07-19 2007-02-01 Shinko Electric Ind Co Ltd 回路基板及びその製造方法

Also Published As

Publication number Publication date
EP2056343A2 (en) 2009-05-06
US20090121345A1 (en) 2009-05-14
JP2009111120A (ja) 2009-05-21
KR20090045012A (ko) 2009-05-07
EP2056343A3 (en) 2011-09-21
US7851359B2 (en) 2010-12-14

Similar Documents

Publication Publication Date Title
JP5311609B2 (ja) シリコンインターポーザの製造方法およびシリコンインターポーザと、これを用いた半導体装置用パッケージおよび半導体装置
JP5248084B2 (ja) シリコンインターポーザとこれを用いた半導体装置用パッケージおよび半導体装置
JP5808586B2 (ja) インターポーザの製造方法
JP4361826B2 (ja) 半導体装置
US7135765B2 (en) Semiconductor device package and method of making the same
TWI278048B (en) Semiconductor device and its manufacturing method
US8319115B2 (en) Wiring board and manufacturing method thereof
CN100556246C (zh) 配线基板的制造方法
JP5389770B2 (ja) 電子素子内蔵印刷回路基板及びその製造方法
US20070178686A1 (en) Interconnect substrate, semiconductor device, and method of manufacturing the same
US9338886B2 (en) Substrate for mounting semiconductor, semiconductor device and method for manufacturing semiconductor device
JP2001177010A (ja) 配線基板、配線基板を有する半導体装置、及び、その製造方法、実装方法
JP4345808B2 (ja) 半導体装置の製造方法
JP2002164467A (ja) 回路ブロック体及びその製造方法、配線回路装置及びその製造方法並びに半導体装置及びその製造方法
US10256117B2 (en) Manufacturing method and wiring substrate with through electrode
JP6444269B2 (ja) 電子部品装置及びその製造方法
US10129980B2 (en) Circuit board and electronic component device
JP4070470B2 (ja) 半導体装置用多層回路基板及びその製造方法並びに半導体装置
JP5272922B2 (ja) 半導体装置及びその製造方法
US9281269B2 (en) Integrated circuit package and method of manufacture
JP5058929B2 (ja) 配線基板およびその製造方法
JP4407702B2 (ja) 表裏導通基板の製造方法および表裏導電基板
JP3589928B2 (ja) 半導体装置
JP2007158078A (ja) 半導体装置とその製造方法
JP2003163240A (ja) 半導体装置およびその製造方法

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20100730

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20100730

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20110104

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20120724

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20120920

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20121016

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20130701

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

Ref document number: 5311609

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150