JP5268305B2 - 半導体装置の作製方法 - Google Patents

半導体装置の作製方法 Download PDF

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Publication number
JP5268305B2
JP5268305B2 JP2007217762A JP2007217762A JP5268305B2 JP 5268305 B2 JP5268305 B2 JP 5268305B2 JP 2007217762 A JP2007217762 A JP 2007217762A JP 2007217762 A JP2007217762 A JP 2007217762A JP 5268305 B2 JP5268305 B2 JP 5268305B2
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Japan
Prior art keywords
semiconductor film
semiconductor
semiconductor films
substrate
film
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Expired - Fee Related
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JP2007217762A
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English (en)
Japanese (ja)
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JP2009054661A (ja
JP2009054661A5 (enExample
Inventor
舜平 山崎
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Semiconductor Energy Laboratory Co Ltd
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Semiconductor Energy Laboratory Co Ltd
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Application filed by Semiconductor Energy Laboratory Co Ltd filed Critical Semiconductor Energy Laboratory Co Ltd
Priority to JP2007217762A priority Critical patent/JP5268305B2/ja
Priority to US12/222,891 priority patent/US7829396B2/en
Publication of JP2009054661A publication Critical patent/JP2009054661A/ja
Publication of JP2009054661A5 publication Critical patent/JP2009054661A5/ja
Priority to US12/939,500 priority patent/US8268701B2/en
Application granted granted Critical
Publication of JP5268305B2 publication Critical patent/JP5268305B2/ja
Expired - Fee Related legal-status Critical Current
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0214—Manufacture or treatment of multiple TFTs using temporary substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67144—Apparatus for mounting on conductive members, e.g. leadframes or conductors on insulating substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H10D86/425—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer having different crystal properties in different TFTs or within an individual TFT
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H10D30/0323—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon comprising monocrystalline silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Thin Film Transistor (AREA)
  • Liquid Crystal (AREA)
  • Electroluminescent Light Sources (AREA)
  • Element Separation (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
JP2007217762A 2007-08-24 2007-08-24 半導体装置の作製方法 Expired - Fee Related JP5268305B2 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2007217762A JP5268305B2 (ja) 2007-08-24 2007-08-24 半導体装置の作製方法
US12/222,891 US7829396B2 (en) 2007-08-24 2008-08-19 Manufacturing method of semiconductor device and manufacturing apparatus of the same
US12/939,500 US8268701B2 (en) 2007-08-24 2010-11-04 Manufacturing of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2007217762A JP5268305B2 (ja) 2007-08-24 2007-08-24 半導体装置の作製方法

Publications (3)

Publication Number Publication Date
JP2009054661A JP2009054661A (ja) 2009-03-12
JP2009054661A5 JP2009054661A5 (enExample) 2010-09-30
JP5268305B2 true JP5268305B2 (ja) 2013-08-21

Family

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JP2007217762A Expired - Fee Related JP5268305B2 (ja) 2007-08-24 2007-08-24 半導体装置の作製方法

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US (2) US7829396B2 (enExample)
JP (1) JP5268305B2 (enExample)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9115538B2 (en) * 2007-06-07 2015-08-25 Vkr Holding A/S Screening device with an electronic motion sensor
JP5460984B2 (ja) 2007-08-17 2014-04-02 株式会社半導体エネルギー研究所 半導体装置の作製方法
JP5268305B2 (ja) 2007-08-24 2013-08-21 株式会社半導体エネルギー研究所 半導体装置の作製方法
US8232598B2 (en) * 2007-09-20 2012-07-31 Semiconductor Energy Laboratory Co., Ltd. Display device and method for manufacturing the same
JP5288966B2 (ja) * 2008-09-22 2013-09-11 ユー・ディー・シー アイルランド リミテッド 発光素子及びその製造方法、並びに該発光素子を備えるディスプレイ
WO2011158438A1 (ja) * 2010-06-14 2011-12-22 シャープ株式会社 半導体装置の製造方法、及び表示装置の製造方法
KR101145074B1 (ko) * 2010-07-02 2012-05-11 이상윤 반도체 기판의 제조 방법 및 이를 이용한 반도체 장치의 제조 방법
CN102719251B (zh) * 2012-06-12 2014-06-11 北京工业大学 一种下转换发光增强复合粉体材料及其制备方法
TWI463620B (zh) * 2012-08-22 2014-12-01 矽品精密工業股份有限公司 封裝基板之製法
JP6515537B2 (ja) * 2014-04-08 2019-05-22 セイコーエプソン株式会社 有機ｅｌ装置の製造方法、有機ｅｌ装置、電子機器
JP6390898B2 (ja) * 2014-08-22 2018-09-19 アイシン精機株式会社 基板の製造方法、加工対象物の切断方法、及び、レーザ加工装置
CN110620055B (zh) * 2019-09-23 2021-06-25 九江市海纳电讯技术有限公司 一种rf射频装置的键合方法

Family Cites Families (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63169760A (ja) * 1987-01-07 1988-07-13 Mitsubishi Electric Corp 半導体装置の製造方法
JPH0590117A (ja) 1991-09-27 1993-04-09 Toshiba Corp 単結晶薄膜半導体装置
JPH07297377A (ja) 1994-04-21 1995-11-10 Mitsubishi Electric Corp 半導体装置およびその製造方法
EP1655633A3 (en) 1996-08-27 2006-06-21 Seiko Epson Corporation Exfoliating method, transferring method of thin film device, thin film integrated circuit device, and liquid crystal display device
JP2000012864A (ja) 1998-06-22 2000-01-14 Semiconductor Energy Lab Co Ltd 半導体装置の作製方法
JP3432187B2 (ja) 1999-09-22 2003-08-04 シャープ株式会社 半導体装置の製造方法
US20020031909A1 (en) 2000-05-11 2002-03-14 Cyril Cabral Self-aligned silicone process for low resistivity contacts to thin film silicon-on-insulator mosfets
JP4708577B2 (ja) 2001-01-31 2011-06-22 キヤノン株式会社 薄膜半導体装置の製造方法
JP4800524B2 (ja) 2001-09-10 2011-10-26 ルネサスエレクトロニクス株式会社 半導体装置の製造方法、及び、製造装置
WO2003049189A1 (en) 2001-12-04 2003-06-12 Shin-Etsu Handotai Co.,Ltd. Pasted wafer and method for producing pasted wafer
JP4151420B2 (ja) 2003-01-23 2008-09-17 セイコーエプソン株式会社 デバイスの製造方法
US6964201B2 (en) * 2003-02-25 2005-11-15 Palo Alto Research Center Incorporated Large dimension, flexible piezoelectric ceramic tapes
JP3927165B2 (ja) 2003-07-03 2007-06-06 株式会社東芝 半導体装置
US6821826B1 (en) 2003-09-30 2004-11-23 International Business Machines Corporation Three dimensional CMOS integrated circuits having device layers built on different crystal oriented wafers
DE102004031708B4 (de) 2004-06-30 2008-02-07 Advanced Micro Devices, Inc., Sunnyvale Verfahren zum Herstellen eines Substrats mit kristallinen Halbleitergebieten unterschiedlicher Eigenschaften
KR100539271B1 (ko) 2004-07-26 2005-12-27 삼성전자주식회사 휨 방지 재질을 사용하는 반도체 칩의 다이 접착 방법
US7312487B2 (en) 2004-08-16 2007-12-25 International Business Machines Corporation Three dimensional integrated circuit
JP4078562B2 (ja) * 2004-08-23 2008-04-23 セイコーエプソン株式会社 圧電薄膜共振子の製造方法、圧電薄膜共振子、周波数フィルタ、発振器の製造方法、発振器、電子回路、および電子機器
JP4838504B2 (ja) * 2004-09-08 2011-12-14 キヤノン株式会社 半導体装置の製造方法
US7298009B2 (en) 2005-02-01 2007-11-20 Infineon Technologies Ag Semiconductor method and device with mixed orientation substrate
FR2888402B1 (fr) 2005-07-06 2007-12-21 Commissariat Energie Atomique Procede d'assemblage de substrats par depot d'une couche mince de collage d'oxyde ou de nitrure et structure ainsi assemblee
US7696574B2 (en) * 2005-10-26 2010-04-13 International Business Machines Corporation Semiconductor substrate with multiple crystallographic orientations
US7288458B2 (en) * 2005-12-14 2007-10-30 Freescale Semiconductor, Inc. SOI active layer with different surface orientation
JP4380709B2 (ja) 2007-01-31 2009-12-09 セイコーエプソン株式会社 半導体装置の製造方法
KR101461206B1 (ko) 2007-05-17 2014-11-12 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체장치 및 그의 제조방법
JP5460984B2 (ja) 2007-08-17 2014-04-02 株式会社半導体エネルギー研究所 半導体装置の作製方法
JP5268305B2 (ja) 2007-08-24 2013-08-21 株式会社半導体エネルギー研究所 半導体装置の作製方法

Also Published As

Publication number Publication date
US20090053876A1 (en) 2009-02-26
US8268701B2 (en) 2012-09-18
JP2009054661A (ja) 2009-03-12
US7829396B2 (en) 2010-11-09
US20110045655A1 (en) 2011-02-24

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