FR2888402B1 - Procede d'assemblage de substrats par depot d'une couche mince de collage d'oxyde ou de nitrure et structure ainsi assemblee - Google Patents

Procede d'assemblage de substrats par depot d'une couche mince de collage d'oxyde ou de nitrure et structure ainsi assemblee

Info

Publication number
FR2888402B1
FR2888402B1 FR0507206A FR0507206A FR2888402B1 FR 2888402 B1 FR2888402 B1 FR 2888402B1 FR 0507206 A FR0507206 A FR 0507206A FR 0507206 A FR0507206 A FR 0507206A FR 2888402 B1 FR2888402 B1 FR 2888402B1
Authority
FR
France
Prior art keywords
depositing
assembled
bonding layer
thin oxide
assembling substrates
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR0507206A
Other languages
English (en)
Other versions
FR2888402A1 (fr
Inventor
Cioccio Lea Di
Marek Kostrzewa
Marc Zussy
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
Original Assignee
Commissariat a lEnergie Atomique CEA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Commissariat a lEnergie Atomique CEA filed Critical Commissariat a lEnergie Atomique CEA
Priority to FR0507206A priority Critical patent/FR2888402B1/fr
Priority to PCT/FR2006/001596 priority patent/WO2007006914A1/fr
Priority to EP06778776A priority patent/EP1900020A1/fr
Priority to US11/994,636 priority patent/US20080311725A1/en
Priority to JP2008518928A priority patent/JP2009500819A/ja
Publication of FR2888402A1 publication Critical patent/FR2888402A1/fr
Application granted granted Critical
Publication of FR2888402B1 publication Critical patent/FR2888402B1/fr
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/27—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
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    • H01L2924/01057—Lanthanum [La]
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    • H01L2924/049—Nitrides composed of metals from groups of the periodic table
    • H01L2924/0495—5th Group
    • H01L2924/04953—TaN
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    • H01L2924/06—Polymers
    • H01L2924/0665—Epoxy resin
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    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
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    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
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    • H01L2924/10329—Gallium arsenide [GaAs]
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Element Separation (AREA)
  • Pressure Welding/Diffusion-Bonding (AREA)
  • Recrystallisation Techniques (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
FR0507206A 2005-07-06 2005-07-06 Procede d'assemblage de substrats par depot d'une couche mince de collage d'oxyde ou de nitrure et structure ainsi assemblee Expired - Fee Related FR2888402B1 (fr)

Priority Applications (5)

Application Number Priority Date Filing Date Title
FR0507206A FR2888402B1 (fr) 2005-07-06 2005-07-06 Procede d'assemblage de substrats par depot d'une couche mince de collage d'oxyde ou de nitrure et structure ainsi assemblee
PCT/FR2006/001596 WO2007006914A1 (fr) 2005-07-06 2006-07-05 Procede d'assemblage de substrats par depot d'une couche mince de collage d'oxyde ou de nitrure
EP06778776A EP1900020A1 (fr) 2005-07-06 2006-07-05 Procede d'assemblage de substrats par depot d'une couche mince de collage d'oxyde ou de nitrure
US11/994,636 US20080311725A1 (en) 2005-07-06 2006-07-05 Method For Assembling Substrates By Depositing An Oxide Or Nitride Thin Bonding Layer
JP2008518928A JP2009500819A (ja) 2005-07-06 2006-07-05 酸化物もしくは窒化物の薄い結合層を堆積することによる基板の組み立て方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0507206A FR2888402B1 (fr) 2005-07-06 2005-07-06 Procede d'assemblage de substrats par depot d'une couche mince de collage d'oxyde ou de nitrure et structure ainsi assemblee

Publications (2)

Publication Number Publication Date
FR2888402A1 FR2888402A1 (fr) 2007-01-12
FR2888402B1 true FR2888402B1 (fr) 2007-12-21

Family

ID=36021781

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0507206A Expired - Fee Related FR2888402B1 (fr) 2005-07-06 2005-07-06 Procede d'assemblage de substrats par depot d'une couche mince de collage d'oxyde ou de nitrure et structure ainsi assemblee

Country Status (5)

Country Link
US (1) US20080311725A1 (fr)
EP (1) EP1900020A1 (fr)
JP (1) JP2009500819A (fr)
FR (1) FR2888402B1 (fr)
WO (1) WO2007006914A1 (fr)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5460984B2 (ja) 2007-08-17 2014-04-02 株式会社半導体エネルギー研究所 半導体装置の作製方法
JP5268305B2 (ja) 2007-08-24 2013-08-21 株式会社半導体エネルギー研究所 半導体装置の作製方法
FR2926747B1 (fr) * 2008-01-25 2011-01-14 Commissariat Energie Atomique Objet comportant un element graphique reporte sur un support et procede de realisation d'un tel objet.
FR2926748B1 (fr) * 2008-01-25 2010-04-02 Commissariat Energie Atomique Objet muni d'un element graphique reporte sur un support et procede de realisation d'un tel objet.
FR2946435B1 (fr) 2009-06-04 2017-09-29 Commissariat A L'energie Atomique Procede de fabrication d'images colorees avec une resolution micronique enfouies dans un support tres robuste et tres perenne
FR2948318B1 (fr) * 2009-07-22 2011-08-19 Commissariat Energie Atomique Procede de realisation d'un dispositif a element graphique
WO2011132654A1 (fr) * 2010-04-20 2011-10-27 住友電気工業株式会社 Procédé de production d'un substrat composite
FR2967016B1 (fr) * 2010-11-08 2012-12-07 Commissariat Energie Atomique Procédé de réalisation d'une pièce contenant un motif enfoui dont les dimensions sont au plus micrométriques, et pièce ainsi obtenue
US9227295B2 (en) 2011-05-27 2016-01-05 Corning Incorporated Non-polished glass wafer, thinning system and method for using the non-polished glass wafer to thin a semiconductor wafer
CN108281378B (zh) * 2012-10-12 2022-06-24 住友电气工业株式会社 Iii族氮化物复合衬底、半导体器件及它们的制造方法
CN111146141A (zh) * 2019-12-13 2020-05-12 中国科学院微电子研究所 一种片上单晶材料的制备方法

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06112451A (ja) * 1992-09-29 1994-04-22 Nagano Denshi Kogyo Kk Ｓｏｉ基板の製造方法
KR20010029456A (ko) * 1996-09-04 2001-04-06 시본드 엘.엘.씨 본딩된 반도체 기판에 대한 평탄화 공정
US6902987B1 (en) * 2000-02-16 2005-06-07 Ziptronix, Inc. Method for low temperature bonding and bonded structure
US6537846B2 (en) * 2001-03-30 2003-03-25 Hewlett-Packard Development Company, L.P. Substrate bonding using a selenidation reaction
US6562127B1 (en) * 2002-01-16 2003-05-13 The United States Of America As Represented By The Secretary Of The Navy Method of making mosaic array of thin semiconductor material of large substrates
US6995430B2 (en) * 2002-06-07 2006-02-07 Amberwave Systems Corporation Strained-semiconductor-on-insulator device structures
US20040126993A1 (en) * 2002-12-30 2004-07-01 Chan Kevin K. Low temperature fusion bonding with high surface energy using a wet chemical treatment
FR2851079B1 (fr) * 2003-02-12 2005-08-26 Soitec Silicon On Insulator Structure semi-conductrice sur substrat a forte rugosite
FR2857982B1 (fr) * 2003-07-24 2007-05-18 Soitec Silicon On Insulator Procede de fabrication d'une couche epitaxiee
US20080211061A1 (en) * 2004-04-21 2008-09-04 California Institute Of Technology Method For the Fabrication of GaAs/Si and Related Wafer Bonded Virtual Substrates
JP2005347302A (ja) * 2004-05-31 2005-12-15 Canon Inc 基板の製造方法

Also Published As

Publication number Publication date
FR2888402A1 (fr) 2007-01-12
WO2007006914A1 (fr) 2007-01-18
US20080311725A1 (en) 2008-12-18
EP1900020A1 (fr) 2008-03-19
JP2009500819A (ja) 2009-01-08

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