JP5265852B2 - マルチビット不揮発性メモリセルを含む半導体素子及びその製造方法 - Google Patents
マルチビット不揮発性メモリセルを含む半導体素子及びその製造方法 Download PDFInfo
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- JP5265852B2 JP5265852B2 JP2005315324A JP2005315324A JP5265852B2 JP 5265852 B2 JP5265852 B2 JP 5265852B2 JP 2005315324 A JP2005315324 A JP 2005315324A JP 2005315324 A JP2005315324 A JP 2005315324A JP 5265852 B2 JP5265852 B2 JP 5265852B2
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
- G11C16/0475—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] comprising two or more independent storage sites which store independent data
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
- G11C16/0441—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates
- G11C16/0458—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates comprising two or more independent floating gates which store independent data
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5692—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency read-only digital stores using storage elements with more than two stable states
Description
I=(1/Leff)K(VG−VT)
CSR1,CSR2,・・・,CSRn:電荷蓄積領域
CV1,CV2,・・・,CVn:コントロール電圧
D:ドレーン
I1,I2,・・・,In:電流
S:ソース
T1,T2,・・・,Tn:トランジスタ
Claims (15)
- 基板上に一方向に延長されて形成された複数の半導体ボディー;
前記半導体ボディーの周りに沿って前記半導体ボディー内に形成された複数のチャネル領域;
前記チャネル領域上に形成された電荷蓄積領域;
前記電荷蓄積領域上に形成され、独立的に電圧が印加される複数のコントロールゲート;および
前記複数のコントロールゲートの両側に整列されて前記各半導体ボディー内に形成されたソース及びドレーン領域を備える複数のマルチビット不揮発性メモリ単位セル;
を含み、
前記複数のコントロールゲートは、前記半導体ボディーの両側壁に整列されて、前記半導体ボディー間の空間全体を埋めるように形成された複数の側壁コントロールゲート、及び前記複数の半導体ボディーと前記複数の側壁コントロールゲートとの上面上に絶縁膜を介して形成された複数の上面コントロールゲートを含み、前記複数の上面コントロールゲートは前記一方向と異なる他方向に延長されて形成されることを特徴とする不揮発性半導体素子。 - 前記半導体ボディーは、前記基板の主面に垂直である両側壁及び前記基板の主面に平行な上面を備えるメサ形態に突出されたボディーであることを特徴とする請求項1に記載の不揮発性半導体素子。
- 前記側壁コントロールゲートそれぞれの電流駆動力が異なることを特徴とする請求項1に記載の不揮発性半導体素子。
- 前記ドレーン領域に検出される電流が0レベル〜7レベルであることを特徴とする請求項3に記載の不揮発性半導体素子。
- 前記半導体ボディーの前記側壁の高さと前記半導体ボディーの上面の幅が異なり、
前記側壁コントロールゲートの幅が相異なることを特徴とする請求項3に記載の不揮発性半導体素子。 - 前記側壁コントロールゲートと前記上面コントロールゲート下部の電荷蓄積領域を構成するトンネリング絶縁膜の厚さが異なり、
前記側壁コントロールゲートの幅が相異なることを特徴とする請求項3に記載の不揮発性半導体素子。 - 前記側壁コントロールゲートそれぞれの電流駆動力が同一なことを特徴とする請求項1に記載の不揮発性半導体素子。
- 前記側壁コントロールゲート及び前記上面コントロールゲートは、電流駆動力が同一なことを特徴とする請求項1に記載の不揮発性半導体素子。
- 前記上面コントロールゲートには、前記側壁コントロールゲートの上面の前記絶縁膜を露出させる開口部を含むことを特徴とする請求項1に記載の不揮発性半導体素子。
- 前記側壁コントロールゲートは、それぞれスペーサ形態に形成されたことを特徴とする請求項1に記載の不揮発性半導体素子。
- 前記電荷蓄積領域は、フローティングトラップ構造又はフローティングゲート構造より成ったことを特徴とする請求項1に記載の不揮発性半導体素子。
- 前記フローティングトラップ構造は、トンネリング絶縁膜、電荷トラップ膜、ブロッキング絶縁膜の積層構造であることを特徴とする請求項11に記載の不揮発性半導体素子。
- 前記ソースを共有し、前記ソースを中心に対称に配列された他の前記単位セルをさらに含むことを特徴とする請求項1に記載の不揮発性半導体素子。
- 一方向に延長されて形成された複数の平行な半導体ボディーと前記一方向と垂直な他方向に延長されて形成された複数の平行な半導体ボディーが互いに連結されて成されたグリッド形態の半導体ボディー;
前記一方向に延長されて形成された3次元半導体ボディーの周りに沿って前記3次元半導体ボディーの一部領域内に形成された複数のチャネル領域;
前記チャネル領域上に形成された電荷蓄積領域;
前記電荷蓄積領域上に形成され、独立的に電圧が印加される複数のコントロールゲート;および
前記複数のコントロールゲートの両側に整列されて前記各半導体ボディー内に形成されたソース及びドレーン領域をそれぞれ備えるマルチビット不揮発性メモリ単位セルの対と、
を含み、
前記複数のコントロールゲートは、前記一方向に延長されて形成された前記半導体ボディーの両側壁に整列されて、前記半導体ボディー間の空間全体を埋めるように形成された複数の側壁コントロールゲート、及び前記複数の半導体ボディーと前記複数の側壁コントロールゲートとの上面上に絶縁膜を介して形成された複数の上面コントロールゲートを含み、前記複数の上面コントロールゲートは前記他方向に延長されて形成され、
前記単位セルの対は、前記ソース領域を共有し、前記ソース領域は前記グリッドの交差点に形成されるメモリセルアレイを含むことを特徴とする不揮発性半導体素子。 - 基板上に一方向に延長されて形成された複数の半導体ボディーを形成する段階;
前記半導体ボディーの周りに沿って前記半導体ボディー内に複数のチャネル領域を形成する段階;
前記チャネル領域上に電荷蓄積領域を形成する段階;
前記電荷蓄積領域上に独立的に電圧が印加される複数のコントロールゲートを形成する段階;および
前記各半導体ボディー内に前記複数のコントロールゲートの両側に整列されたソース及びドレーン領域を形成する段階;
を含み、
前記複数のコントロールゲートを形成する段階は、
前記半導体ボディーの両側壁に整列されて、前記半導体ボディー間の空間全体を埋めるように形成された複数の側壁コントロールゲートを形成する段階;前記複数の半導体ボディーと前記複数の側壁コントロールゲートとの上面上に絶縁膜を形成する段階;及び前記絶縁膜の上面上に前記一方向と異なる他方向に延長される複数の上面コントロールゲートを形成する段階;を含むことを特徴とする不揮発性半導体素子の製造方法。
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KR1020040086765A KR100598049B1 (ko) | 2004-10-28 | 2004-10-28 | 멀티 비트 비휘발성 메모리 셀을 포함하는 반도체 소자 및그 제조 방법 |
KR10-2004-0086765 | 2004-10-28 |
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US (2) | US7339232B2 (ja) |
JP (1) | JP5265852B2 (ja) |
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DE (1) | DE102005052272B4 (ja) |
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KR100546405B1 (ko) * | 2004-03-18 | 2006-01-26 | 삼성전자주식회사 | 스플릿 게이트형 비휘발성 반도체 메모리 소자 및 그제조방법 |
US7312495B2 (en) * | 2005-04-07 | 2007-12-25 | Spansion Llc | Split gate multi-bit memory cell |
US7132329B1 (en) * | 2005-06-29 | 2006-11-07 | Freescale Semiconductor, Inc. | Source side injection storage device with spacer gates and method therefor |
KR100668350B1 (ko) * | 2005-12-20 | 2007-01-12 | 삼성전자주식회사 | 낸드 구조의 멀티-비트 비휘발성 메모리 소자 및 그 제조방법 |
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US20060092705A1 (en) | 2006-05-04 |
DE102005052272A1 (de) | 2006-06-01 |
US7521750B2 (en) | 2009-04-21 |
US7339232B2 (en) | 2008-03-04 |
KR100598049B1 (ko) | 2006-07-07 |
JP2006128703A (ja) | 2006-05-18 |
US20080137417A1 (en) | 2008-06-12 |
KR20060037722A (ko) | 2006-05-03 |
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