JP5263811B2 - 集積回路パッケージシステムおよびその製造方法 - Google Patents

集積回路パッケージシステムおよびその製造方法 Download PDF

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Publication number
JP5263811B2
JP5263811B2 JP2007327757A JP2007327757A JP5263811B2 JP 5263811 B2 JP5263811 B2 JP 5263811B2 JP 2007327757 A JP2007327757 A JP 2007327757A JP 2007327757 A JP2007327757 A JP 2007327757A JP 5263811 B2 JP5263811 B2 JP 5263811B2
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Prior art keywords
integrated circuit
die
stack
circuit die
lower die
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JP2007327757A
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Japanese (ja)
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JP2008160119A5 (https=
JP2008160119A (ja
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チェ・ケオン・チン
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Stats Chippac Pte Ltd
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Stats Chippac Pte Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5445—Dispositions of bond wires being orthogonal to a side surface of the chip, e.g. parallel arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/547—Dispositions of multiple bond wires
    • H10W72/5473—Dispositions of multiple bond wires multiple bond wires connected to a common bond pad
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5522—Materials of bond wires comprising metals or metalloids, e.g. silver comprising gold [Au]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5524—Materials of bond wires comprising metals or metalloids, e.g. silver comprising aluminium [Al]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/231—Configurations of stacked chips the stacked chips being on both top and bottom sides of an auxiliary carrier having no electrical connection structure
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/24—Configurations of stacked chips at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/732—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/752—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Die Bonding (AREA)
JP2007327757A 2006-12-20 2007-12-19 集積回路パッケージシステムおよびその製造方法 Active JP5263811B2 (ja)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US87113406P 2006-12-20 2006-12-20
US60/871,134 2006-12-20
US11/950,216 2007-12-04
US11/950,216 US8242607B2 (en) 2006-12-20 2007-12-04 Integrated circuit package system with offset stacked die and method of manufacture thereof

Publications (3)

Publication Number Publication Date
JP2008160119A JP2008160119A (ja) 2008-07-10
JP2008160119A5 JP2008160119A5 (https=) 2011-06-02
JP5263811B2 true JP5263811B2 (ja) 2013-08-14

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Application Number Title Priority Date Filing Date
JP2007327757A Active JP5263811B2 (ja) 2006-12-20 2007-12-19 集積回路パッケージシステムおよびその製造方法

Country Status (4)

Country Link
US (1) US8242607B2 (https=)
JP (1) JP5263811B2 (https=)
KR (1) KR101485972B1 (https=)
TW (1) TWI499028B (https=)

Families Citing this family (40)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8704379B2 (en) 2007-09-10 2014-04-22 Invensas Corporation Semiconductor die mount by conformal die coating
JP4498403B2 (ja) * 2007-09-28 2010-07-07 株式会社東芝 半導体装置と半導体記憶装置
KR100886717B1 (ko) * 2007-10-16 2009-03-04 주식회사 하이닉스반도체 적층 반도체 패키지 및 이의 제조 방법
TWI415201B (zh) * 2007-11-30 2013-11-11 矽品精密工業股份有限公司 多晶片堆疊結構及其製法
JP5150243B2 (ja) * 2007-12-27 2013-02-20 株式会社東芝 半導体記憶装置
JP5207868B2 (ja) 2008-02-08 2013-06-12 ルネサスエレクトロニクス株式会社 半導体装置
US8178978B2 (en) 2008-03-12 2012-05-15 Vertical Circuits, Inc. Support mounted electrically interconnected die assembly
US9153517B2 (en) 2008-05-20 2015-10-06 Invensas Corporation Electrical connector between die pad and z-interconnect for stacked die assemblies
JP4776675B2 (ja) * 2008-10-31 2011-09-21 株式会社東芝 半導体メモリカード
KR20100049283A (ko) * 2008-11-03 2010-05-12 삼성전자주식회사 반도체 패키지 및 그 제조 방법
JP5126002B2 (ja) * 2008-11-11 2013-01-23 セイコーエプソン株式会社 半導体装置及び半導体装置の製造方法
KR101013563B1 (ko) * 2009-02-25 2011-02-14 주식회사 하이닉스반도체 스택 패키지
KR20100134354A (ko) * 2009-06-15 2010-12-23 삼성전자주식회사 반도체 패키지, 스택 모듈, 카드 및 전자 시스템
CN102473697B (zh) * 2009-06-26 2016-08-10 伊文萨思公司 曲折配置的堆叠裸片的电互连
KR101026488B1 (ko) * 2009-08-10 2011-04-01 주식회사 하이닉스반도체 반도체 패키지
KR101563630B1 (ko) * 2009-09-17 2015-10-28 에스케이하이닉스 주식회사 반도체 패키지
US8552546B2 (en) * 2009-10-06 2013-10-08 Samsung Electronics Co., Ltd. Semiconductor package, semiconductor package structure including the semiconductor package, and mobile phone including the semiconductor package structure
KR20110044077A (ko) * 2009-10-22 2011-04-28 삼성전자주식회사 반도체 패키지 구조물
WO2011056668A2 (en) 2009-10-27 2011-05-12 Vertical Circuits, Inc. Selective die electrical insulation additive process
CN103098206A (zh) * 2010-03-18 2013-05-08 莫塞德技术公司 具有偏移裸片叠层的多芯片封装及其制造方法
KR20110138789A (ko) * 2010-06-22 2011-12-28 하나 마이크론(주) 적층형 반도체 패키지
US8502375B2 (en) 2010-06-29 2013-08-06 Sandisk Technologies Inc. Corrugated die edge for stacked die semiconductor package
KR101686553B1 (ko) * 2010-07-12 2016-12-14 삼성전자 주식회사 반도체 패키지 및 패키지 온 패키지
KR20120024099A (ko) * 2010-09-06 2012-03-14 삼성전자주식회사 멀티-칩 패키지 및 그의 제조 방법
KR101213288B1 (ko) 2011-01-25 2012-12-18 하나 마이크론(주) 계단식 적층구조를 갖는 반도체 패키지 및 그의 제조방법
WO2013071399A1 (en) * 2011-11-14 2013-05-23 Mosaid Technologies Incorporated Package having stacked memory dies with serially connected buffer dies
CN104769714B (zh) 2013-02-26 2018-10-26 晟碟信息科技（上海）有限公司 包括交替形成台阶的半导体裸芯堆叠的半导体器件
US9412722B1 (en) * 2015-02-12 2016-08-09 Dawning Leading Technology Inc. Multichip stacking package structure and method for manufacturing the same
US9825002B2 (en) 2015-07-17 2017-11-21 Invensas Corporation Flipped die stack
US9490195B1 (en) 2015-07-17 2016-11-08 Invensas Corporation Wafer-level flipped die stacks with leadframes or metal foil interconnects
US9871019B2 (en) 2015-07-17 2018-01-16 Invensas Corporation Flipped die stack assemblies with leadframe interconnects
WO2017095401A1 (en) 2015-12-02 2017-06-08 Intel Corporation Die stack with cascade and vertical connections
US9508691B1 (en) 2015-12-16 2016-11-29 Invensas Corporation Flipped die stacks with multiple rows of leadframe interconnects
US10566310B2 (en) 2016-04-11 2020-02-18 Invensas Corporation Microelectronic packages having stacked die and wire bond interconnects
US9595511B1 (en) 2016-05-12 2017-03-14 Invensas Corporation Microelectronic packages and assemblies with improved flyby signaling operation
US9728524B1 (en) 2016-06-30 2017-08-08 Invensas Corporation Enhanced density assembly having microelectronic packages mounted at substantial angle to board
JP2019161095A (ja) * 2018-03-15 2019-09-19 東芝メモリ株式会社 半導体装置
US11139283B2 (en) * 2018-12-22 2021-10-05 Xcelsis Corporation Abstracted NAND logic in stacks
US11282814B2 (en) 2019-12-27 2022-03-22 Micron Technology, Inc. Semiconductor device assemblies including stacked individual modules
KR20230166701A (ko) * 2022-05-31 2023-12-07 삼성전자주식회사 반도체 패키지 및 이의 제조 방법

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3007023B2 (ja) * 1995-05-30 2000-02-07 シャープ株式会社 半導体集積回路およびその製造方法
US6621155B1 (en) * 1999-12-23 2003-09-16 Rambus Inc. Integrated circuit device having stacked dies and impedance balanced transmission lines
US6376904B1 (en) * 1999-12-23 2002-04-23 Rambus Inc. Redistributed bond pads in stacked integrated circuit die package
JP3768761B2 (ja) 2000-01-31 2006-04-19 株式会社日立製作所 半導体装置およびその製造方法
KR100335717B1 (ko) * 2000-02-18 2002-05-08 윤종용 고용량 메모리 카드
JP3813788B2 (ja) 2000-04-14 2006-08-23 株式会社ルネサステクノロジ 半導体装置及びその製造方法
JP2002359346A (ja) 2001-05-30 2002-12-13 Sharp Corp 半導体装置および半導体チップの積層方法
US6900528B2 (en) * 2001-06-21 2005-05-31 Micron Technology, Inc. Stacked mass storage flash memory package
US7045887B2 (en) * 2002-10-08 2006-05-16 Chippac, Inc. Semiconductor multi-package module having inverted second package stacked over die-up flip-chip ball grid array (BGA) package
DE102004049356B4 (de) * 2004-10-08 2006-06-29 Infineon Technologies Ag Halbleitermodul mit einem internen Halbleiterchipstapel und Verfahren zur Herstellung desselben
JP4674113B2 (ja) 2005-05-06 2011-04-20 Ｏｋｉセミコンダクタ株式会社 半導体装置及びその製造方法
TWI255492B (en) * 2005-05-25 2006-05-21 Siliconware Precision Industries Co Ltd Multi-chip stack structure
US20060267173A1 (en) * 2005-05-26 2006-11-30 Sandisk Corporation Integrated circuit package having stacked integrated circuits and method therefor
US20070085184A1 (en) * 2005-10-13 2007-04-19 Stats Chippac Ltd. Stacked die packaging system
US8710675B2 (en) * 2006-02-21 2014-04-29 Stats Chippac Ltd. Integrated circuit package system with bonding lands

Also Published As

Publication number Publication date
US8242607B2 (en) 2012-08-14
KR101485972B1 (ko) 2015-01-23
TWI499028B (zh) 2015-09-01
US20080150158A1 (en) 2008-06-26
TW200832672A (en) 2008-08-01
KR20080058186A (ko) 2008-06-25
JP2008160119A (ja) 2008-07-10

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