JP5250418B2 - ラインエッジ粗さを低減させた特徴のエッチング - Google Patents

ラインエッジ粗さを低減させた特徴のエッチング Download PDF

Info

Publication number
JP5250418B2
JP5250418B2 JP2008526963A JP2008526963A JP5250418B2 JP 5250418 B2 JP5250418 B2 JP 5250418B2 JP 2008526963 A JP2008526963 A JP 2008526963A JP 2008526963 A JP2008526963 A JP 2008526963A JP 5250418 B2 JP5250418 B2 JP 5250418B2
Authority
JP
Japan
Prior art keywords
layer
photoresist
sidewall
etching
deposition
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2008526963A
Other languages
English (en)
Japanese (ja)
Other versions
JP2009505421A5 (https=
JP2009505421A (ja
Inventor
サジャディ・エス．・エム．・レザ
ハドソン・エリック・エー．
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Lam Research Corp
Original Assignee
Lam Research Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lam Research Corp filed Critical Lam Research Corp
Publication of JP2009505421A publication Critical patent/JP2009505421A/ja
Publication of JP2009505421A5 publication Critical patent/JP2009505421A5/ja
Application granted granted Critical
Publication of JP5250418B2 publication Critical patent/JP5250418B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/26—Processing photosensitive materials; Apparatus therefor
    • G03F7/40—Treatment after imagewise removal, e.g. baking
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/26—Processing photosensitive materials; Apparatus therefor
    • G03F7/40—Treatment after imagewise removal, e.g. baking
    • G03F7/405—Treatment with inorganic or organometallic reagents after imagewise removal
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/26—Processing photosensitive materials; Apparatus therefor
    • G03F7/42—Stripping or agents therefor
    • G03F7/427—Stripping or agents therefor using plasma means only
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/73—Etching of wafers, substrates or parts of devices using masks for insulating materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/20—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials
    • H10P76/204—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials of organic photoresist masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
    • H10P76/408—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes
    • H10P76/4085—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes characterised by the processes involved to create the masks

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Organic Chemistry (AREA)
  • Engineering & Computer Science (AREA)
  • Plasma & Fusion (AREA)
  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
JP2008526963A 2005-08-18 2006-08-01 ラインエッジ粗さを低減させた特徴のエッチング Active JP5250418B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/208,098 2005-08-18
US11/208,098 US7273815B2 (en) 2005-08-18 2005-08-18 Etch features with reduced line edge roughness
PCT/US2006/030028 WO2007021540A2 (en) 2005-08-18 2006-08-01 Etch features with reduced line edge roughness

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2013023716A Division JP2013110437A (ja) 2005-08-18 2013-02-08 ラインエッジ粗さを低減させた特徴のエッチング

Publications (3)

Publication Number Publication Date
JP2009505421A JP2009505421A (ja) 2009-02-05
JP2009505421A5 JP2009505421A5 (https=) 2009-09-10
JP5250418B2 true JP5250418B2 (ja) 2013-07-31

Family

ID=37758048

Family Applications (2)

Application Number Title Priority Date Filing Date
JP2008526963A Active JP5250418B2 (ja) 2005-08-18 2006-08-01 ラインエッジ粗さを低減させた特徴のエッチング
JP2013023716A Withdrawn JP2013110437A (ja) 2005-08-18 2013-02-08 ラインエッジ粗さを低減させた特徴のエッチング

Family Applications After (1)

Application Number Title Priority Date Filing Date
JP2013023716A Withdrawn JP2013110437A (ja) 2005-08-18 2013-02-08 ラインエッジ粗さを低減させた特徴のエッチング

Country Status (6)

Country Link
US (2) US7273815B2 (https=)
JP (2) JP5250418B2 (https=)
KR (1) KR101257532B1 (https=)
CN (2) CN101292197A (https=)
TW (1) TWI432605B (https=)
WO (1) WO2007021540A2 (https=)

Families Citing this family (34)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7250371B2 (en) * 2003-08-26 2007-07-31 Lam Research Corporation Reduction of feature critical dimensions
US20060134917A1 (en) * 2004-12-16 2006-06-22 Lam Research Corporation Reduction of etch mask feature critical dimensions
US7273815B2 (en) * 2005-08-18 2007-09-25 Lam Research Corporation Etch features with reduced line edge roughness
US7682516B2 (en) * 2005-10-05 2010-03-23 Lam Research Corporation Vertical profile fixing
US7309646B1 (en) * 2006-10-10 2007-12-18 Lam Research Corporation De-fluoridation process
JP5108489B2 (ja) * 2007-01-16 2012-12-26 株式会社日立ハイテクノロジーズ プラズマ処理方法
US8592318B2 (en) 2007-11-08 2013-11-26 Lam Research Corporation Pitch reduction using oxide spacer
WO2009085564A2 (en) * 2007-12-21 2009-07-09 Lam Research Corporation Etch with high etch rate resist mask
CN101903978B (zh) * 2007-12-21 2014-11-19 朗姆研究公司 用于注入光刻胶的保护层
US8753804B2 (en) * 2008-03-11 2014-06-17 Lam Research Corporation Line width roughness improvement with noble gas plasma
US7772122B2 (en) * 2008-09-18 2010-08-10 Lam Research Corporation Sidewall forming processes
US8921726B2 (en) * 2009-02-06 2014-12-30 Lg Chem, Ltd. Touch screen and manufacturing method thereof
KR20170048609A (ko) * 2009-04-09 2017-05-08 램 리써치 코포레이션 감소된 손상을 갖는 로우-ｋ 유전체 에칭을 위한 방법
US8304262B2 (en) * 2011-02-17 2012-11-06 Lam Research Corporation Wiggling control for pseudo-hardmask
US20130078804A1 (en) * 2011-09-22 2013-03-28 Nanya Technology Corporation Method for fabricating integrated devices with reducted plasma damage
US20140162194A1 (en) * 2012-05-25 2014-06-12 Applied Materials, Inc. Conformal sacrificial film by low temperature chemical vapor deposition technique
CN103871956A (zh) * 2012-12-10 2014-06-18 中微半导体设备(上海)有限公司 一种深孔硅刻蚀方法
CN104157556B (zh) * 2013-05-15 2017-08-25 中芯国际集成电路制造(上海)有限公司 金属硬掩模开口刻蚀方法
US8883648B1 (en) * 2013-09-09 2014-11-11 United Microelectronics Corp. Manufacturing method of semiconductor structure
CN104465386A (zh) * 2013-09-24 2015-03-25 中芯国际集成电路制造(北京)有限公司 半导体结构的形成方法
CN104275171B (zh) * 2014-06-18 2016-07-20 河海大学 一种二氧化硅纳米层包覆的γ-氧化铝粉体材料的制备方法
JP6239466B2 (ja) * 2014-08-15 2017-11-29 東京エレクトロン株式会社 半導体装置の製造方法
CN105719965A (zh) * 2014-12-04 2016-06-29 北京北方微电子基地设备工艺研究中心有限责任公司 二氧化硅基片的刻蚀方法和刻蚀设备
CN106158595B (zh) * 2015-04-20 2019-03-12 中芯国际集成电路制造(上海)有限公司 半导体器件的形成方法
US9543203B1 (en) 2015-07-02 2017-01-10 United Microelectronics Corp. Method of fabricating a semiconductor structure with a self-aligned contact
KR20170016107A (ko) 2015-08-03 2017-02-13 삼성전자주식회사 반도체 장치 제조 방법
US20180323078A1 (en) * 2015-12-24 2018-11-08 Intel Corporation Pitch division using directed self-assembly
US9852924B1 (en) * 2016-08-24 2017-12-26 Lam Research Corporation Line edge roughness improvement with sidewall sputtering
CN107527797B (zh) * 2017-08-16 2022-04-05 江苏鲁汶仪器有限公司 一种改善光刻胶线条边缘粗糙度的方法
US20190378725A1 (en) * 2018-06-08 2019-12-12 Lam Research Corporation Method for transferring a pattern from an organic mask
JP7357528B2 (ja) * 2019-12-06 2023-10-06 東京エレクトロン株式会社 エッチング方法及びエッチング装置
KR20250044885A (ko) * 2022-07-29 2025-04-01 도쿄엘렉트론가부시키가이샤 기판 처리 방법 및 기판 처리 시스템
US20250062124A1 (en) * 2023-08-18 2025-02-20 Tokyo Electron Limited Methods and structures for improving etch profile of underlying layers
CN117936376B (zh) * 2024-03-25 2024-06-07 上海谙邦半导体设备有限公司 一种碳化硅沟槽的刻蚀方法及碳化硅半导体器件

Family Cites Families (46)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5378170A (en) * 1976-12-22 1978-07-11 Toshiba Corp Continuous processor for gas plasma etching
US4871630A (en) * 1986-10-28 1989-10-03 International Business Machines Corporation Mask using lithographic image size reduction
US5013680A (en) * 1990-07-18 1991-05-07 Micron Technology, Inc. Process for fabricating a DRAM array having feature widths that transcend the resolution limit of available photolithography
US5273609A (en) * 1990-09-12 1993-12-28 Texas Instruments Incorporated Method and apparatus for time-division plasma chopping in a multi-channel plasma processing equipment
DE4241045C1 (de) * 1992-12-05 1994-05-26 Bosch Gmbh Robert Verfahren zum anisotropen Ätzen von Silicium
US5296410A (en) * 1992-12-16 1994-03-22 Samsung Electronics Co., Ltd. Method for separating fine patterns of a semiconductor device
JPH06216084A (ja) * 1992-12-17 1994-08-05 Samsung Electron Co Ltd 半導体装置のパターン分離方法および微細パターン形成方法
JPH0997833A (ja) * 1995-07-22 1997-04-08 Ricoh Co Ltd 半導体装置とその製造方法
US5879853A (en) * 1996-01-18 1999-03-09 Kabushiki Kaisha Toshiba Top antireflective coating material and its process for DUV and VUV lithography systems
US5741626A (en) * 1996-04-15 1998-04-21 Motorola, Inc. Method for forming a dielectric tantalum nitride layer as an anti-reflective coating (ARC)
GB9616225D0 (en) * 1996-08-01 1996-09-11 Surface Tech Sys Ltd Method of surface treatment of semiconductor substrates
US5895740A (en) * 1996-11-13 1999-04-20 Vanguard International Semiconductor Corp. Method of forming contact holes of reduced dimensions by using in-situ formed polymeric sidewall spacers
US5907775A (en) * 1997-04-11 1999-05-25 Vanguard International Semiconductor Corporation Non-volatile memory device with high gate coupling ratio and manufacturing process therefor
SE512813C2 (sv) * 1997-05-23 2000-05-15 Ericsson Telefon Ab L M Förfarande för framställning av en integrerad krets innefattande en dislokationsfri kollektorplugg förbunden med en begravd kollektor i en halvledarkomponent, som är omgiven av en dislokationsfri trench samt integrerad krets framställd enligt förfarandet
US6187685B1 (en) * 1997-08-01 2001-02-13 Surface Technology Systems Limited Method and apparatus for etching a substrate
US6218288B1 (en) * 1998-05-11 2001-04-17 Micron Technology, Inc. Multiple step methods for forming conformal layers
US6100014A (en) * 1998-11-24 2000-08-08 United Microelectronics Corp. Method of forming an opening in a dielectric layer through a photoresist layer with silylated sidewall spacers
JP2001015587A (ja) * 1999-06-30 2001-01-19 Toshiba Corp 半導体装置の製造方法
US6368974B1 (en) * 1999-08-02 2002-04-09 United Microelectronics Corp. Shrinking equal effect critical dimension of mask by in situ polymer deposition and etching
JP2002110654A (ja) * 2000-10-04 2002-04-12 Sony Corp 半導体装置の製造方法
US6905800B1 (en) * 2000-11-21 2005-06-14 Stephen Yuen Etching a substrate in a process zone
US6656282B2 (en) * 2001-10-11 2003-12-02 Moohan Co., Ltd. Atomic layer deposition apparatus and process using remote plasma
US6750150B2 (en) * 2001-10-18 2004-06-15 Macronix International Co., Ltd. Method for reducing dimensions between patterns on a photoresist
KR100448714B1 (ko) * 2002-04-24 2004-09-13 삼성전자주식회사 다층 나노라미네이트 구조를 갖는 반도체 장치의 절연막및 그의 형성방법
US7105442B2 (en) * 2002-05-22 2006-09-12 Applied Materials, Inc. Ashable layers for reducing critical dimensions of integrated circuit features
US20030235998A1 (en) * 2002-06-24 2003-12-25 Ming-Chung Liang Method for eliminating standing waves in a photoresist profile
US20040010769A1 (en) * 2002-07-12 2004-01-15 Macronix International Co., Ltd. Method for reducing a pitch of a procedure
KR100480610B1 (ko) * 2002-08-09 2005-03-31 삼성전자주식회사 실리콘 산화막을 이용한 미세 패턴 형성방법
US7169695B2 (en) * 2002-10-11 2007-01-30 Lam Research Corporation Method for forming a dual damascene structure
US7090967B2 (en) * 2002-12-30 2006-08-15 Infineon Technologies Ag Pattern transfer in device fabrication
US6780708B1 (en) * 2003-03-05 2004-08-24 Advanced Micro Devices, Inc. Method of forming core and periphery gates including two critical masking steps to form a hard mask in a core region that includes a critical dimension less than achievable at a resolution limit of lithography
US6829056B1 (en) * 2003-08-21 2004-12-07 Michael Barnes Monitoring dimensions of features at different locations in the processing of substrates
US7250371B2 (en) * 2003-08-26 2007-07-31 Lam Research Corporation Reduction of feature critical dimensions
JP4727171B2 (ja) * 2003-09-29 2011-07-20 東京エレクトロン株式会社 エッチング方法
KR100549204B1 (ko) * 2003-10-14 2006-02-02 주식회사 리드시스템 실리콘 이방성 식각 방법
US7012027B2 (en) * 2004-01-27 2006-03-14 Taiwan Semiconductor Manufacturing Company, Ltd. Zirconium oxide and hafnium oxide etching using halogen containing chemicals
US6864184B1 (en) * 2004-02-05 2005-03-08 Advanced Micro Devices, Inc. Method for reducing critical dimension attainable via the use of an organic conforming layer
US20060032833A1 (en) * 2004-08-10 2006-02-16 Applied Materials, Inc. Encapsulation of post-etch halogenic residue
US7723235B2 (en) * 2004-09-17 2010-05-25 Renesas Technology Corp. Method for smoothing a resist pattern prior to etching a layer using the resist pattern
US20060134917A1 (en) * 2004-12-16 2006-06-22 Lam Research Corporation Reduction of etch mask feature critical dimensions
US7271107B2 (en) * 2005-02-03 2007-09-18 Lam Research Corporation Reduction of feature critical dimensions using multiple masks
US20070026682A1 (en) * 2005-02-10 2007-02-01 Hochberg Michael J Method for advanced time-multiplexed etching
US7491647B2 (en) * 2005-03-08 2009-02-17 Lam Research Corporation Etch with striation control
KR100810303B1 (ko) * 2005-04-28 2008-03-06 삼성전자주식회사 휴대단말기의 데이터 표시 및 전송방법
US7695632B2 (en) * 2005-05-31 2010-04-13 Lam Research Corporation Critical dimension reduction and roughness control
US7273815B2 (en) * 2005-08-18 2007-09-25 Lam Research Corporation Etch features with reduced line edge roughness

Also Published As

Publication number Publication date
US20070284690A1 (en) 2007-12-13
WO2007021540A2 (en) 2007-02-22
US20070042607A1 (en) 2007-02-22
CN103105744A (zh) 2013-05-15
JP2009505421A (ja) 2009-02-05
TW200720482A (en) 2007-06-01
TWI432605B (zh) 2014-04-01
JP2013110437A (ja) 2013-06-06
KR101257532B1 (ko) 2013-04-23
KR20080046665A (ko) 2008-05-27
US7273815B2 (en) 2007-09-25
CN101292197A (zh) 2008-10-22
WO2007021540A3 (en) 2007-12-21

Similar Documents

Publication Publication Date Title
JP5250418B2 (ja) ラインエッジ粗さを低減させた特徴のエッチング
KR101534883B1 (ko) 마스크 트리밍
US7491647B2 (en) Etch with striation control
JP5048055B2 (ja) エッチング層内に特徴を設けるための方法
JP5165560B2 (ja) エッチング層に形状を形成するための方法
JP5165306B2 (ja) 多孔質低ｋ誘電体層内に特徴を形成するための装置
JP5632280B2 (ja) 異なるアスペクト比の構成を誘電層内にエッチングするための方法、及びその方法によって作成される半導体デバイス、並びにそのための装置
KR101516455B1 (ko) Ａｒｌ 에칭을 이용한 마스크 트리밍
US7977242B2 (en) Double mask self-aligned double patterning technology (SADPT) process
JP2012175105A (ja) 疑似ハードマスクのためのウィグリング制御
JP2013016844A (ja) 均一性を制御したエッチング
WO2007092114A1 (en) Reducing line edge roughness
TWI393997B (zh) 用於蝕刻基板上之低k介電層的方法、半導體裝置以及用於在低k介電層中形成特徵的設備

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20090723

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20090723

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20100405

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20120110

A601 Written request for extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A601

Effective date: 20120409

A602 Written permission of extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A602

Effective date: 20120416

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20120710

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20121009

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20130208

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A821

Effective date: 20130212

A911 Transfer to examiner for re-examination before appeal (zenchi)

Free format text: JAPANESE INTERMEDIATE CODE: A911

Effective date: 20130305

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20130326

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20130415

R150 Certificate of patent or registration of utility model

Ref document number: 5250418

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20160419

Year of fee payment: 3

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250