JP5234884B2 - 樹脂封止金型 - Google Patents
樹脂封止金型 Download PDFInfo
- Publication number
- JP5234884B2 JP5234884B2 JP2006342683A JP2006342683A JP5234884B2 JP 5234884 B2 JP5234884 B2 JP 5234884B2 JP 2006342683 A JP2006342683 A JP 2006342683A JP 2006342683 A JP2006342683 A JP 2006342683A JP 5234884 B2 JP5234884 B2 JP 5234884B2
- Authority
- JP
- Japan
- Prior art keywords
- resin
- mold
- cavity
- substrate
- lower mold
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Moulds For Moulding Plastics Or The Like (AREA)
- Injection Moulding Of Plastics Or The Like (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Description
110…基板
110A…硬質層
110B…レジスト層
112…ウィンドウ
114…ボンディングワイヤ
116…はんだボール取付部
120…半導体チップ
150…上型(第1の金型)
150A…上型キャビティ
160…下型(第2の金型)
160A…下型キャビティ
162…凹部
164…凸部
166…凹凸部
H1…レジスト層厚
H2…凸部高さ
D1…下型キャビティ厚
D2…凹部深さ
Claims (5)
- 第1の金型と第2の金型の双方に樹脂が充填されるキャビティを有し、当該第1の金型側のキャビティから当該第2の金型側のキャビティへと前記樹脂を案内可能な貫通孔を有した基板を該第1、第2の金型でクランプした上で当該基板の両面を樹脂にて封止する樹脂封止金型であって、
前記第2の金型側のキャビティは前記第1の金型側のキャビティよりも面積が小さく、且つ該第2の金型側のキャビティの周囲部は前記樹脂を介して前記第1の金型に支持され、
前記第2の金型のクランプ面には、前記第2の金型側のキャビティの周囲部で該キャビティを取り囲む態様で少なくとも一組の凹凸部が形成されている
ことを特徴とする樹脂封止金型。 - 請求項1において、
前記凹凸部が、前記第2の金型側のキャビティの周囲に途切れることなく形成されている
ことを特徴とする樹脂封止金型。 - 請求項1又は2において、
前記凹凸部は、内周側に凹部が、外周側に凸部が配置されて形成されている
ことを特徴とする樹脂封止金型。 - 請求項1乃至3のいずれかにおいて、
前記基板の表面に、電気的絶縁を保つレジスト層が設けられ、
前記凸部の最上部と前記クランプ面との高さの差が、前記レジスト層の厚み以下である
ことを特徴とする樹脂封止金型。 - 請求項1乃至4のいずれかにおいて、
前記凹部の底と前記クランプ面との高さの差が、前記第2の金型側のキャビティの厚み以下である
ことを特徴とする樹脂封止金型。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006342683A JP5234884B2 (ja) | 2006-12-20 | 2006-12-20 | 樹脂封止金型 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006342683A JP5234884B2 (ja) | 2006-12-20 | 2006-12-20 | 樹脂封止金型 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2008149677A JP2008149677A (ja) | 2008-07-03 |
JP5234884B2 true JP5234884B2 (ja) | 2013-07-10 |
Family
ID=39652387
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2006342683A Expired - Fee Related JP5234884B2 (ja) | 2006-12-20 | 2006-12-20 | 樹脂封止金型 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP5234884B2 (ja) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5969883B2 (ja) * | 2012-10-03 | 2016-08-17 | 信越化学工業株式会社 | 半導体装置の製造方法 |
JPWO2015174198A1 (ja) * | 2014-05-13 | 2017-04-20 | 三菱電機株式会社 | 半導体装置とその製造方法 |
WO2020157965A1 (ja) * | 2019-02-01 | 2020-08-06 | 三菱電機株式会社 | 半導体装置およびその製造方法ならびに電力変換装置 |
JP7444711B2 (ja) | 2020-06-24 | 2024-03-06 | 株式会社日立製作所 | パワーモジュール及びこれを用いた電力変換装置 |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS501662A (ja) * | 1973-05-07 | 1975-01-09 | ||
JPS55138239A (en) * | 1979-04-11 | 1980-10-28 | Yamagata Nippon Denki Kk | Resin sealing mold |
JPS6215827A (ja) * | 1985-07-12 | 1987-01-24 | Matsushita Electric Ind Co Ltd | 封止金型装置 |
JPS63155632U (ja) * | 1987-03-31 | 1988-10-12 | ||
JPH01192146A (ja) * | 1988-01-27 | 1989-08-02 | Mitsubishi Electric Corp | 半導体装置用基板 |
JPH0510361Y2 (ja) * | 1988-08-22 | 1993-03-15 | ||
JPH058106Y2 (ja) * | 1988-11-11 | 1993-03-01 | ||
JPH07232352A (ja) * | 1994-02-24 | 1995-09-05 | Nec Kansai Ltd | 樹脂モールド装置 |
JP2531382B2 (ja) * | 1994-05-26 | 1996-09-04 | 日本電気株式会社 | ボ―ルグリッドアレイ半導体装置およびその製造方法 |
JPH10242344A (ja) * | 1997-03-03 | 1998-09-11 | Yamaha Motor Co Ltd | 電力用半導体装置 |
-
2006
- 2006-12-20 JP JP2006342683A patent/JP5234884B2/ja not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JP2008149677A (ja) | 2008-07-03 |
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