JP5230542B2 - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法 Download PDF

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Publication number
JP5230542B2
JP5230542B2 JP2009148054A JP2009148054A JP5230542B2 JP 5230542 B2 JP5230542 B2 JP 5230542B2 JP 2009148054 A JP2009148054 A JP 2009148054A JP 2009148054 A JP2009148054 A JP 2009148054A JP 5230542 B2 JP5230542 B2 JP 5230542B2
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JP
Japan
Prior art keywords
film
semiconductor device
manufacturing
wiring
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2009148054A
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English (en)
Japanese (ja)
Other versions
JP2011003859A (ja
JP2011003859A5 (https=
Inventor
剛史 原田
潤一 柴田
彰 植木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Corp
Panasonic Holdings Corp
Original Assignee
Panasonic Corp
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Panasonic Corp, Matsushita Electric Industrial Co Ltd filed Critical Panasonic Corp
Priority to JP2009148054A priority Critical patent/JP5230542B2/ja
Priority to PCT/JP2010/000444 priority patent/WO2010150430A1/ja
Publication of JP2011003859A publication Critical patent/JP2011003859A/ja
Publication of JP2011003859A5 publication Critical patent/JP2011003859A5/ja
Priority to US13/274,039 priority patent/US8927416B2/en
Application granted granted Critical
Publication of JP5230542B2 publication Critical patent/JP5230542B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/425—Barrier, adhesion or liner layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/033—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics
    • H10W20/037—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics the barrier, adhesion or liner layers being on top of a main fill metal
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H10W20/077—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers on sidewalls or on top surfaces of conductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/093—Manufacture or treatment of dielectric parts thereof by modifying materials of the dielectric parts
    • H10W20/096—Manufacture or treatment of dielectric parts thereof by modifying materials of the dielectric parts by contacting with gases, liquids or plasmas
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/45—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
    • H10W20/47—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts comprising two or more dielectric layers having different properties, e.g. different dielectric constants

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Plasma & Fusion (AREA)
JP2009148054A 2009-06-22 2009-06-22 半導体装置の製造方法 Expired - Fee Related JP5230542B2 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2009148054A JP5230542B2 (ja) 2009-06-22 2009-06-22 半導体装置の製造方法
PCT/JP2010/000444 WO2010150430A1 (ja) 2009-06-22 2010-01-27 半導体装置及びその製造方法
US13/274,039 US8927416B2 (en) 2009-06-22 2011-10-14 Semiconductor device and method of manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2009148054A JP5230542B2 (ja) 2009-06-22 2009-06-22 半導体装置の製造方法

Publications (3)

Publication Number Publication Date
JP2011003859A JP2011003859A (ja) 2011-01-06
JP2011003859A5 JP2011003859A5 (https=) 2011-08-18
JP5230542B2 true JP5230542B2 (ja) 2013-07-10

Family

ID=43386221

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009148054A Expired - Fee Related JP5230542B2 (ja) 2009-06-22 2009-06-22 半導体装置の製造方法

Country Status (3)

Country Link
US (1) US8927416B2 (https=)
JP (1) JP5230542B2 (https=)
WO (1) WO2010150430A1 (https=)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160276156A1 (en) * 2015-03-16 2016-09-22 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and manufacturing process thereof
US9673091B2 (en) * 2015-06-25 2017-06-06 Globalfoundries Inc. Structure for BEOL metal levels with multiple dielectric layers for improved dielectric to metal adhesion
DE102019131408B4 (de) 2019-06-28 2025-12-04 Taiwan Semiconductor Manufacturing Company, Ltd. Verbesserte Kontaktierung von Metallleitungen bei Fehlausrichtung von BEOL-Durchkontaktierungen
CN112151497B (zh) 2019-06-28 2023-08-22 台湾积体电路制造股份有限公司 半导体结构以及形成半导体结构的方法
US12272600B2 (en) * 2022-01-12 2025-04-08 Taiwan Semiconductor Manufacturing Co., Ltd. Contact features of semiconductor device and method of forming same
CN115732405A (zh) * 2022-09-20 2023-03-03 长鑫存储技术有限公司 半导体结构的形成方法及半导体结构

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW379387B (en) 1996-11-29 2000-01-11 Texas Instruments Inc A process for encapsulation of copper surfaces
US6448655B1 (en) * 1998-04-28 2002-09-10 International Business Machines Corporation Stabilization of fluorine-containing low-k dielectrics in a metal/insulator wiring structure by ultraviolet irradiation
JP2000058544A (ja) * 1998-08-04 2000-02-25 Matsushita Electron Corp 半導体装置及びその製造方法
JP4535629B2 (ja) * 2001-02-21 2010-09-01 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
JP4063619B2 (ja) * 2002-03-13 2008-03-19 Ｎｅｃエレクトロニクス株式会社 半導体装置の製造方法
US20050250346A1 (en) * 2004-05-06 2005-11-10 Applied Materials, Inc. Process and apparatus for post deposition treatment of low k dielectric materials
KR100703973B1 (ko) * 2005-07-20 2007-04-06 삼성전자주식회사 이중 캡핑막을 갖는 반도체 소자의 배선 및 그 형성 방법
JP2009016502A (ja) * 2007-07-03 2009-01-22 Tdk Corp ワイヤ被膜剥離方法、コイル部品の製造方法、ワイヤ被膜剥離装置およびコイル部品の製造装置
JP2009016520A (ja) * 2007-07-04 2009-01-22 Tokyo Electron Ltd 半導体装置の製造方法及び半導体装置の製造装置

Also Published As

Publication number Publication date
JP2011003859A (ja) 2011-01-06
US8927416B2 (en) 2015-01-06
US20120032333A1 (en) 2012-02-09
WO2010150430A1 (ja) 2010-12-29

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