JP5227412B2 - 半導体基板における格子欠陥の抑制方法 - Google Patents
半導体基板における格子欠陥の抑制方法 Download PDFInfo
- Publication number
- JP5227412B2 JP5227412B2 JP2010529994A JP2010529994A JP5227412B2 JP 5227412 B2 JP5227412 B2 JP 5227412B2 JP 2010529994 A JP2010529994 A JP 2010529994A JP 2010529994 A JP2010529994 A JP 2010529994A JP 5227412 B2 JP5227412 B2 JP 5227412B2
- Authority
- JP
- Japan
- Prior art keywords
- compressed
- layer
- atoms
- lattice
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 230000007547 defect Effects 0.000 title claims description 39
- 239000004065 semiconductor Substances 0.000 title claims description 22
- 238000000034 method Methods 0.000 title claims description 20
- 239000000758 substrate Substances 0.000 title claims description 13
- 230000006835 compression Effects 0.000 claims description 24
- 238000007906 compression Methods 0.000 claims description 24
- 239000002019 doping agent Substances 0.000 claims description 14
- 239000013078 crystal Substances 0.000 claims description 10
- 238000002513 implantation Methods 0.000 claims description 8
- 229910052710 silicon Inorganic materials 0.000 claims description 8
- 239000010703 silicon Substances 0.000 claims description 8
- 229910052732 germanium Inorganic materials 0.000 claims description 5
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 5
- 238000000137 annealing Methods 0.000 claims description 4
- 238000004519 manufacturing process Methods 0.000 claims description 4
- 230000007935 neutral effect Effects 0.000 claims 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 230000015572 biosynthetic process Effects 0.000 description 5
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000010849 ion bombardment Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000000737 periodic effect Effects 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/107—Substrate region of field-effect devices
- H01L29/1075—Substrate region of field-effect devices of field-effect transistors
- H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- High Energy & Nuclear Physics (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Description
Claims (18)
- 結晶基板上における半導体の製造時に、結晶格子におけるドーパント注入後に、リークを促進する欠陥が前記格子に形成されるのを抑制する方法であって、
前記半導体は、ソース領域及びドレイン領域と、前記ソース領域と前記ドレイン領域の間に位置するチャネルと、前記チャネルの上に位置するゲートと、前記各領域に隣接する空乏層を備え、
前記方法は、
前記結晶格子に圧縮応力を印加するように選択された原子である圧縮原子からなる圧縮層を提供する工程と、
格子間欠陥原子が前記圧縮層から放出されるのに十分な時間、前記格子をアニールする工程と、を備え、それにより、
エネルギー的に安定した欠陥が、前記圧縮層から離間して前記格子内に形成されることを特徴とする方法。 - 前記圧縮原子が、前記格子を構成する原子よりも大きいことを特徴とする請求項1に記載の方法。
- 前記圧縮原子が、電気的に中性であることを特徴とする請求項1に記載の方法。
- 前記圧縮層が、前記圧縮原子をドーパント原子と共に注入することによって形成されることを特徴とする請求項1に記載の方法。
- 前記圧縮層が、エピタキシャル成長によって形成されることを特徴とする請求項1に記載の方法。
- 前記格子を構成する原子がシリコンであり、前記圧縮原子がゲルマニウムであることを特徴とする請求項1に記載の方法。
- 前記圧縮層が、前記空乏層内の少なくとも一部に設けられていることを特徴とする請求項1に記載の方法。
- 前記圧縮層が、前記空乏層の外側で、かつ、前記空乏層と前記欠陥の間に設けられていることを特徴とする請求項1に記載の方法。
- 前記圧縮層が、前記空乏層よりも浅いところに設けられており、前記欠陥が前記ソース領域と前記ドレイン領域にあることを特徴とする請求項1に記載の方法。
- 結晶基板上に形成された半導体であって、
前記半導体は、ソース領域及びドレイン領域と、前記ソース領域と前記ドレイン領域の間に位置するチャネルと、前記チャネルの上に位置するゲートと、前記各領域に隣接する空乏層と、前記結晶格子に圧縮応力を印加するように選択された原子である圧縮原子からなる圧縮層を備え、
存在するエネルギー的に安定した格子間欠陥が何れも、前記圧縮層の外側にあることを特徴とする半導体。 - 前記圧縮原子が、前記格子を構成する原子よりも大きいことを特徴とする請求項10に記載の半導体。
- 前記圧縮原子が、電気的に中性であることを特徴とする請求項10に記載の半導体。
- 前記圧縮層が、前記圧縮原子をドーパント原子と共に注入することによって形成されることを特徴とする請求項10に記載の半導体。
- 前記圧縮層が、エピタキシャル成長によって形成されることを特徴とする請求項10に記載の半導体。
- 前記格子を構成する原子がシリコンであり、前記圧縮原子がゲルマニウムであることを特徴とする請求項10に記載の半導体。
- 前記圧縮層が、前記空乏層内の少なくとも一部に設けられていることを特徴とする請求項10に記載の半導体。
- 前記圧縮層が、前記空乏層の外側で、かつ、前記空乏層と前記欠陥の間に設けられていることを特徴とする請求項10に記載の半導体。
- 前記圧縮層が、前記空乏層よりも浅いところに設けられており、前記欠陥が前記ソース領域と前記ドレイン領域にあることを特徴とする請求項10に記載の半導体。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/928,142 US9472423B2 (en) | 2007-10-30 | 2007-10-30 | Method for suppressing lattice defects in a semiconductor substrate |
US11/928,142 | 2007-10-30 | ||
PCT/US2008/071572 WO2009058449A1 (en) | 2007-10-30 | 2008-07-30 | Method for suppressing lattice defects in a semiconductor substrate |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2011501437A JP2011501437A (ja) | 2011-01-06 |
JP5227412B2 true JP5227412B2 (ja) | 2013-07-03 |
Family
ID=40581686
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2010529994A Expired - Fee Related JP5227412B2 (ja) | 2007-10-30 | 2008-07-30 | 半導体基板における格子欠陥の抑制方法 |
Country Status (6)
Country | Link |
---|---|
US (2) | US9472423B2 (ja) |
EP (1) | EP2210269A4 (ja) |
JP (1) | JP5227412B2 (ja) |
CN (1) | CN101681838B (ja) |
TW (1) | TWI396236B (ja) |
WO (1) | WO2009058449A1 (ja) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9276113B2 (en) * | 2014-03-10 | 2016-03-01 | International Business Corporation | Structure and method to make strained FinFET with improved junction capacitance and low leakage |
CN112271137B (zh) * | 2020-11-02 | 2024-04-09 | 中国工程物理研究院电子工程研究所 | 一种基于高电子迁移率晶体管的钝化方法 |
Family Cites Families (69)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR910006249B1 (ko) | 1983-04-01 | 1991-08-17 | 가부시기가이샤 히다찌세이사꾸쇼 | 반도체 장치 |
JPH0338044A (ja) | 1989-07-05 | 1991-02-19 | Toshiba Corp | 半導体装置の製造方法 |
US5592012A (en) | 1993-04-06 | 1997-01-07 | Sharp Kabushiki Kaisha | Multivalued semiconductor read only storage device and method of driving the device and method of manufacturing the device |
JPH0878682A (ja) | 1994-07-08 | 1996-03-22 | Hitachi Ltd | 半導体集積回路装置の製造方法 |
US6590230B1 (en) | 1996-10-15 | 2003-07-08 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method thereof |
JPH10270685A (ja) | 1997-03-27 | 1998-10-09 | Sony Corp | 電界効果トランジスタとその製造方法、半導体装置とその製造方法、その半導体装置を含む論理回路および半導体基板 |
TW429478B (en) * | 1997-08-29 | 2001-04-11 | Toshiba Corp | Semiconductor device and method for manufacturing the same |
US5966622A (en) | 1997-10-08 | 1999-10-12 | Lucent Technologies Inc. | Process for bonding crystalline substrates with different crystal lattices |
JPH11168069A (ja) | 1997-12-03 | 1999-06-22 | Nec Corp | 半導体装置の製造方法 |
CN1155074C (zh) | 1998-09-02 | 2004-06-23 | Memc电子材料有限公司 | 从低缺陷密度的单晶硅上制备硅-绝缘体结构 |
US6200869B1 (en) | 1998-11-06 | 2001-03-13 | Advanced Micro Devices, Inc. | Method of fabricating an integrated circuit with ultra-shallow source/drain extensions |
US6225173B1 (en) | 1998-11-06 | 2001-05-01 | Advanced Micro Devices, Inc. | Recessed channel structure for manufacturing shallow source/drain extensions |
US6180476B1 (en) * | 1998-11-06 | 2001-01-30 | Advanced Micro Devices, Inc. | Dual amorphization implant process for ultra-shallow drain and source extensions |
US5985726A (en) | 1998-11-06 | 1999-11-16 | Advanced Micro Devices, Inc. | Damascene process for forming ultra-shallow source/drain extensions and pocket in ULSI MOSFET |
US6618847B1 (en) | 1998-11-13 | 2003-09-09 | Stmicroelectronics, Inc. | Power stabilizer using under-utilized standard cells |
TW533508B (en) * | 1999-05-05 | 2003-05-21 | Taiwan Semiconductor Mfg | Structure and method for preventing inter-metal dielectric layer of semiconductor from cracking |
JP2001144170A (ja) | 1999-11-11 | 2001-05-25 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
JP2001210720A (ja) | 2000-01-27 | 2001-08-03 | Nec Ic Microcomput Syst Ltd | 半導体装置のレイアウト設計方法 |
JP2001237322A (ja) * | 2000-02-25 | 2001-08-31 | Nec Microsystems Ltd | 半導体集積回路のレイアウト方法 |
US6437406B1 (en) | 2000-10-19 | 2002-08-20 | International Business Machines Corporation | Super-halo formation in FETs |
US6594809B2 (en) | 2000-11-29 | 2003-07-15 | Taiwan Semiconductor Manufacturing Co., Ltd. | Low leakage antenna diode insertion for integrated circuits |
US6502229B2 (en) | 2001-03-26 | 2002-12-31 | Oridus, Inc. | Method for inserting antenna diodes into an integrated circuit design |
WO2002080045A2 (en) | 2001-03-28 | 2002-10-10 | California Institute Of Technology | De novo processing of electronic materials |
JP2003128494A (ja) * | 2001-10-22 | 2003-05-08 | Sharp Corp | 半導体装置の製造方法及び半導体装置 |
ITTO20011129A1 (it) | 2001-12-04 | 2003-06-04 | Infm Istituto Naz Per La Fisi | Metodo per la soppressione della diffusione anomala transiente di droganti in silicio. |
CN1444264A (zh) * | 2002-03-08 | 2003-09-24 | 矽统科技股份有限公司 | 微浅绝缘沟槽结构制备法 |
US6689671B1 (en) * | 2002-05-22 | 2004-02-10 | Advanced Micro Devices, Inc. | Low temperature solid-phase epitaxy fabrication process for MOS devices built on strained semiconductor substrate |
JP2004014856A (ja) | 2002-06-07 | 2004-01-15 | Sharp Corp | 半導体基板の製造方法及び半導体装置の製造方法 |
US7302672B2 (en) | 2002-07-12 | 2007-11-27 | Cadence Design Systems, Inc. | Method and system for context-specific mask writing |
CN1259703C (zh) * | 2002-08-29 | 2006-06-14 | 上海宏力半导体制造有限公司 | 改善硅外延层中晶格缺陷的半导体组件制造方法 |
JP2004214440A (ja) * | 2003-01-06 | 2004-07-29 | Matsushita Electric Ind Co Ltd | 半導体装置の製造方法 |
US7032194B1 (en) | 2003-02-19 | 2006-04-18 | Xilinx, Inc. | Layout correction algorithms for removing stress and other physical effect induced process deviation |
DE10310740A1 (de) * | 2003-03-10 | 2004-09-30 | Forschungszentrum Jülich GmbH | Verfahren zur Herstellung einer spannungsrelaxierten Schichtstruktur auf einem nicht gitterangepassten Substrat, sowie Verwendung eines solchen Schichtsystems in elektronischen und/oder optoelektronischen Bauelementen |
JP2004281591A (ja) * | 2003-03-14 | 2004-10-07 | Hitachi Ltd | 半導体エピタキシャルウエハとその製法,半導体装置及びその製法 |
JP4408653B2 (ja) | 2003-05-30 | 2010-02-03 | 東京エレクトロン株式会社 | 基板処理方法および半導体装置の製造方法 |
US6982207B2 (en) | 2003-07-11 | 2006-01-03 | Micron Technology, Inc. | Methods for filling high aspect ratio trenches in semiconductor layers |
US6891192B2 (en) * | 2003-08-04 | 2005-05-10 | International Business Machines Corporation | Structure and method of making strained semiconductor CMOS transistors having lattice-mismatched semiconductor regions underlying source and drain regions |
US7112495B2 (en) | 2003-08-15 | 2006-09-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Structure and method of a strained channel transistor and a second semiconductor component in an integrated circuit |
JP4620942B2 (ja) | 2003-08-21 | 2011-01-26 | 川崎マイクロエレクトロニクス株式会社 | 半導体集積回路のレイアウト方法、そのレイアウト構造、およびフォトマスク |
JP4599048B2 (ja) | 2003-10-02 | 2010-12-15 | 川崎マイクロエレクトロニクス株式会社 | 半導体集積回路のレイアウト構造、半導体集積回路のレイアウト方法、およびフォトマスク |
US6998666B2 (en) | 2004-01-09 | 2006-02-14 | International Business Machines Corporation | Nitrided STI liner oxide for reduced corner device impact on vertical device performance |
US7169675B2 (en) * | 2004-07-07 | 2007-01-30 | Chartered Semiconductor Manufacturing, Ltd | Material architecture for the fabrication of low temperature transistor |
US7316960B2 (en) | 2004-07-13 | 2008-01-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Strain enhanced ultra shallow junction formation |
US7404174B2 (en) | 2004-07-27 | 2008-07-22 | International Business Machines Corporation | method for generating a set of test patterns for an optical proximity correction algorithm |
US7271464B2 (en) | 2004-08-24 | 2007-09-18 | Micron Technology, Inc. | Liner for shallow trench isolation |
US7271443B2 (en) * | 2004-08-25 | 2007-09-18 | Kabushiki Kaisha Toshiba | Semiconductor device and manufacturing method for the same |
JP2006093658A (ja) * | 2004-08-25 | 2006-04-06 | Toshiba Corp | 半導体装置及びその製造方法 |
US7174532B2 (en) | 2004-11-18 | 2007-02-06 | Agere Systems, Inc. | Method of making a semiconductor device by balancing shallow trench isolation stress and optical proximity effects |
US7482255B2 (en) | 2004-12-17 | 2009-01-27 | Houda Graoui | Method of ion implantation to reduce transient enhanced diffusion |
JP2006196872A (ja) * | 2004-12-17 | 2006-07-27 | Matsushita Electric Ind Co Ltd | 標準セル、標準セルライブラリ、半導体装置、及びその配置方法 |
US7538351B2 (en) | 2005-03-23 | 2009-05-26 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for forming an SOI structure with improved carrier mobility and ESD protection |
US20090302349A1 (en) | 2005-06-15 | 2009-12-10 | Industrial Technology Research Institute | Strained germanium field effect transistor and method of fabricating the same |
JP4455441B2 (ja) * | 2005-07-27 | 2010-04-21 | 株式会社東芝 | 半導体装置の製造方法 |
TWI258172B (en) | 2005-08-24 | 2006-07-11 | Ind Tech Res Inst | Transistor device with strained Ge layer by selectively grown and fabricating method thereof |
US7514752B2 (en) * | 2005-08-26 | 2009-04-07 | Toshiba America Electronic Components, Inc. | Reduction of short-circuiting between contacts at or near a tensile-compressive boundary |
JP2007141971A (ja) * | 2005-11-15 | 2007-06-07 | Matsushita Electric Ind Co Ltd | 半導体集積回路の設計方法 |
DE102005057074B4 (de) * | 2005-11-30 | 2009-07-23 | Advanced Micro Devices, Inc., Sunnyvale | Verfahren zum Reduzieren von Kristalldefekten in verformten Transistoren durch eine geneigte Voramorphisierung |
US7543262B2 (en) | 2005-12-06 | 2009-06-02 | Cadence Design Systems, Inc. | Analog layout module generator and method |
US20070160100A1 (en) * | 2006-01-11 | 2007-07-12 | Huffaker Diana L | Misfit dislocation forming interfacial self-assembly for growth of highly-mismatched III-Sb alloys |
US8900980B2 (en) | 2006-01-20 | 2014-12-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Defect-free SiGe source/drain formation by epitaxy-free process |
US7484198B2 (en) | 2006-02-27 | 2009-01-27 | Synopsys, Inc. | Managing integrated circuit stress using dummy diffusion regions |
US7600207B2 (en) | 2006-02-27 | 2009-10-06 | Synopsys, Inc. | Stress-managed revision of integrated circuit layouts |
US7767515B2 (en) | 2006-02-27 | 2010-08-03 | Synopsys, Inc. | Managing integrated circuit stress using stress adjustment trenches |
US7444609B2 (en) | 2006-06-29 | 2008-10-28 | International Business Machines Corporation | Method of optimizing customizable filler cells in an integrated circuit physical design process |
JP5155536B2 (ja) | 2006-07-28 | 2013-03-06 | 一般財団法人電力中央研究所 | SiC結晶の質を向上させる方法およびSiC半導体素子の製造方法 |
US7605407B2 (en) | 2006-09-06 | 2009-10-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Composite stressors with variable element atomic concentrations in MOS devices |
US7521763B2 (en) | 2007-01-03 | 2009-04-21 | International Business Machines Corporation | Dual stress STI |
EP1986237A3 (de) | 2007-04-26 | 2010-09-15 | Atmel Automotive GmbH | Verfahren zur Erzeugung eines Layouts, Verwendung eines Transistorlayouts und Halbleiterschaltung |
US7844936B2 (en) | 2007-08-22 | 2010-11-30 | Infineon Technologies Ag | Method of making an integrated circuit having fill structures |
-
2007
- 2007-10-30 US US11/928,142 patent/US9472423B2/en active Active
-
2008
- 2008-07-30 TW TW097128820A patent/TWI396236B/zh not_active IP Right Cessation
- 2008-07-30 CN CN2008800141375A patent/CN101681838B/zh active Active
- 2008-07-30 WO PCT/US2008/071572 patent/WO2009058449A1/en active Application Filing
- 2008-07-30 JP JP2010529994A patent/JP5227412B2/ja not_active Expired - Fee Related
- 2008-07-30 EP EP08782517A patent/EP2210269A4/en not_active Withdrawn
-
2009
- 2009-10-09 US US12/577,022 patent/US20100025777A1/en not_active Abandoned
Also Published As
Publication number | Publication date |
---|---|
CN101681838B (zh) | 2011-09-14 |
JP2011501437A (ja) | 2011-01-06 |
US20090108293A1 (en) | 2009-04-30 |
EP2210269A1 (en) | 2010-07-28 |
TWI396236B (zh) | 2013-05-11 |
TW200926301A (en) | 2009-06-16 |
US9472423B2 (en) | 2016-10-18 |
CN101681838A (zh) | 2010-03-24 |
EP2210269A4 (en) | 2012-05-30 |
WO2009058449A1 (en) | 2009-05-07 |
US20100025777A1 (en) | 2010-02-04 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR101605150B1 (ko) | 스트레인 유도 합금 및 그레이드형 도펀트 프로파일을 포함하는 인 시츄 형성되는 드레인 및 소스 영역들 | |
US8557692B2 (en) | FinFET LDD and source drain implant technique | |
TWI459557B (zh) | 包含雙應激物的n通道mosfets及其形成方法 | |
US7947546B2 (en) | Implant damage control by in-situ C doping during SiGe epitaxy for device applications | |
US7763505B2 (en) | Method for reducing crystal defects in transistors with re-grown shallow junctions by appropriately selecting crystalline orientations | |
US7767540B2 (en) | Transistor having a channel with tensile strain and oriented along a crystallographic orientation with increased charge carrier mobility | |
US7550336B2 (en) | Method for fabricating an NMOS transistor | |
KR100630767B1 (ko) | 에피택셜 영역을 구비하는 모스 트랜지스터의 제조방법 | |
US8836036B2 (en) | Method for fabricating semiconductor devices using stress engineering | |
US8598006B2 (en) | Strain preserving ion implantation methods | |
TWI578536B (zh) | 半導體元件之製造方法 | |
JP2006019727A (ja) | 勾配付き組み込みシリコン−ゲルマニウムのソース−ドレイン及び/又は延長部をもつ、歪みp型mosfetの構造及びこれを製造する方法 | |
US20080102588A1 (en) | Method for forming mos transistor | |
CN103094207A (zh) | 采用应力记忆技术制造半导体器件的方法 | |
US8273642B2 (en) | Method of fabricating an NMOS transistor | |
US20050136623A1 (en) | Shallow amorphizing implant for gettering of deep secondary end of range defects | |
US7691714B2 (en) | Semiconductor device having a dislocation loop located within a boundary created by source/drain regions and a method of manufacture therefor | |
JP5227412B2 (ja) | 半導体基板における格子欠陥の抑制方法 | |
CN109087859A (zh) | 一种半导体器件的制造方法 | |
US9412869B2 (en) | MOSFET with source side only stress | |
CN112652663B (zh) | Mos晶体管及利用离子注入提高源漏掺杂浓度的方法 | |
US8664073B2 (en) | Method for fabricating field-effect transistor | |
JP2011501438A (ja) | 半導体基板におけるイオン注入損傷のトラップ方法 | |
JP5045048B2 (ja) | 半導体装置の製造方法 | |
CN1531110A (zh) | 半导体装置及其制造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20121031 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20121106 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20130109 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20130219 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20130315 |
|
R150 | Certificate of patent or registration of utility model |
Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20160322 Year of fee payment: 3 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
LAPS | Cancellation because of no payment of annual fees |