JP5225108B2 - ソース／ドレインストレッサ、及び中間誘電体層ストレッサを統合する半導体の製造方法 - Google Patents

ソース／ドレインストレッサ、及び中間誘電体層ストレッサを統合する半導体の製造方法 Download PDF

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JP5225108B2
JP5225108B2 JP2008556494A JP2008556494A JP5225108B2 JP 5225108 B2 JP5225108 B2 JP 5225108B2 JP 2008556494 A JP2008556494 A JP 2008556494A JP 2008556494 A JP2008556494 A JP 2008556494A JP 5225108 B2 JP5225108 B2 JP 5225108B2
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source
drain
stressor
semiconductor
gate
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Japanese (ja)
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JP2009527928A (ja
JP2009527928A5 (enExample
Inventor
チャン、ダ
エイチ． アダムス、バンス
ニュエン、ビチ−エン
エイ． グルダウスキー、ポール
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NXP USA Inc
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NXP USA Inc
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/01—Manufacture or treatment
    • H10D62/021—Forming source or drain recesses by etching e.g. recessing by etching and then refilling
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H10D30/0323—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon comprising monocrystalline silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743—Silicon
    • H10D30/6744—Monocrystalline silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
    • H10D30/792—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions comprising applied insulating layers, e.g. stress liners
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
    • H10D30/795—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions being in lateral device isolation regions, e.g. STI
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
    • H10D30/797—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions being in source or drain regions, e.g. SiGe source or drain
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/82—Heterojunctions
    • H10D62/822—Heterojunctions comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions

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  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
  • Thin Film Transistor (AREA)
JP2008556494A 2006-02-24 2007-02-08 ソース／ドレインストレッサ、及び中間誘電体層ストレッサを統合する半導体の製造方法 Expired - Fee Related JP5225108B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/361,171 2006-02-24
US11/361,171 US7538002B2 (en) 2006-02-24 2006-02-24 Semiconductor process integrating source/drain stressors and interlevel dielectric layer stressors
PCT/US2007/061841 WO2007103609A2 (en) 2006-02-24 2007-02-08 Semiconductor process integrating source/drain stressors and interlevel dielectric layer stressors

Publications (3)

Publication Number Publication Date
JP2009527928A JP2009527928A (ja) 2009-07-30
JP2009527928A5 JP2009527928A5 (enExample) 2010-03-11
JP5225108B2 true JP5225108B2 (ja) 2013-07-03

Family

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Application Number Title Priority Date Filing Date
JP2008556494A Expired - Fee Related JP5225108B2 (ja) 2006-02-24 2007-02-08 ソース／ドレインストレッサ、及び中間誘電体層ストレッサを統合する半導体の製造方法

Country Status (6)

Country Link
US (1) US7538002B2 (enExample)
EP (1) EP1989729B1 (enExample)
JP (1) JP5225108B2 (enExample)
KR (1) KR101357986B1 (enExample)
CN (1) CN101438394B (enExample)
WO (1) WO2007103609A2 (enExample)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
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US7465972B2 (en) 2005-01-21 2008-12-16 Taiwan Semiconductor Manufacturing Company, Ltd. High performance CMOS device design
US7572705B1 (en) * 2005-09-21 2009-08-11 Advanced Micro Devices, Inc. Semiconductor device and method of manufacturing a semiconductor device
US7323392B2 (en) * 2006-03-28 2008-01-29 Taiwan Semiconductor Manufacturing Company, Ltd. High performance transistor with a highly stressed channel
US9209088B2 (en) * 2007-08-01 2015-12-08 Infineon Technologies Ag Semiconductor devices and methods of manufacture thereof
US8003454B2 (en) * 2008-05-22 2011-08-23 Freescale Semiconductor, Inc. CMOS process with optimized PMOS and NMOS transistor devices
US20090289280A1 (en) * 2008-05-22 2009-11-26 Da Zhang Method for Making Transistors and the Device Thereof
JP5163311B2 (ja) * 2008-06-26 2013-03-13 富士通セミコンダクター株式会社 半導体装置及びその製造方法
US8361867B2 (en) * 2010-03-19 2013-01-29 Acorn Technologies, Inc. Biaxial strained field effect transistor devices
US8470674B2 (en) 2011-01-03 2013-06-25 International Business Machines Corporation Structure, method and system for complementary strain fill for integrated circuit chips
CN103377941B (zh) * 2012-04-28 2016-08-10 中芯国际集成电路制造(上海)有限公司 Pmos晶体管及形成方法
JP5712985B2 (ja) * 2012-08-27 2015-05-07 ソニー株式会社 半導体装置
US8928048B2 (en) * 2013-01-17 2015-01-06 Globalfoundries Inc. Methods of forming semiconductor device with self-aligned contact elements and the resulting device
KR102277398B1 (ko) * 2014-09-17 2021-07-16 삼성전자주식회사 반도체 소자 및 이의 제조 방법
US10586866B2 (en) 2015-12-09 2020-03-10 Intel Corporation Stressors for compressively strained GaN p-channel

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6297126B1 (en) 1999-07-12 2001-10-02 Chartered Semiconductor Manufacturing Ltd. Silicon nitride capped shallow trench isolation method for fabricating sub-micron devices with borderless contacts
US6649480B2 (en) * 2000-12-04 2003-11-18 Amberwave Systems Corporation Method of fabricating CMOS inverter and integrated circuits utilizing strained silicon surface channel MOSFETs
US6580122B1 (en) * 2001-03-20 2003-06-17 Advanced Micro Devices, Inc. Transistor device having an enhanced width dimension and a method of making same
JP2005504436A (ja) * 2001-09-21 2005-02-10 アンバーウェーブ システムズ コーポレイション 画定された不純物勾配を有するひずみ材料層を使用する半導体構造、およびその構造を製作するための方法。
US6621131B2 (en) * 2001-11-01 2003-09-16 Intel Corporation Semiconductor transistor having a stressed channel
JP2004031753A (ja) 2002-06-27 2004-01-29 Renesas Technology Corp 半導体装置の製造方法
US7101742B2 (en) * 2003-08-12 2006-09-05 Taiwan Semiconductor Manufacturing Company, Ltd. Strained channel complementary field-effect transistors and methods of manufacture
US7101765B2 (en) * 2004-03-31 2006-09-05 Intel Corporation Enhancing strained device performance by use of multi narrow section layout
US7413957B2 (en) * 2004-06-24 2008-08-19 Applied Materials, Inc. Methods for forming a transistor
US20060022264A1 (en) * 2004-07-30 2006-02-02 Leo Mathew Method of making a double gate semiconductor device with self-aligned gates and structure thereof
US20060030093A1 (en) 2004-08-06 2006-02-09 Da Zhang Strained semiconductor devices and method for forming at least a portion thereof
US6979622B1 (en) 2004-08-24 2005-12-27 Freescale Semiconductor, Inc. Semiconductor transistor having structural elements of differing materials and method of formation
JP4369379B2 (ja) * 2005-02-18 2009-11-18 富士通マイクロエレクトロニクス株式会社 半導体装置
WO2006111888A1 (en) * 2005-04-20 2006-10-26 Koninklijke Philips Electronics N.V. A strained integrated circuit and a method of manufacturing the same

Also Published As

Publication number Publication date
JP2009527928A (ja) 2009-07-30
US7538002B2 (en) 2009-05-26
CN101438394B (zh) 2010-09-08
CN101438394A (zh) 2009-05-20
US20070202651A1 (en) 2007-08-30
KR101357986B1 (ko) 2014-02-03
WO2007103609A3 (en) 2008-12-31
EP1989729A2 (en) 2008-11-12
EP1989729A4 (en) 2011-04-20
EP1989729B1 (en) 2013-04-10
WO2007103609A2 (en) 2007-09-13
KR20080106910A (ko) 2008-12-09

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