JP5219612B2 - 半導体貫通電極形成方法 - Google Patents
半導体貫通電極形成方法 Download PDFInfo
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- JP5219612B2 JP5219612B2 JP2008124122A JP2008124122A JP5219612B2 JP 5219612 B2 JP5219612 B2 JP 5219612B2 JP 2008124122 A JP2008124122 A JP 2008124122A JP 2008124122 A JP2008124122 A JP 2008124122A JP 5219612 B2 JP5219612 B2 JP 5219612B2
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- 239000004065 semiconductor Substances 0.000 title claims description 34
- 238000000034 method Methods 0.000 title claims description 31
- 239000011347 resin Substances 0.000 claims description 94
- 229920005989 resin Polymers 0.000 claims description 94
- 239000000758 substrate Substances 0.000 claims description 27
- 230000015572 biosynthetic process Effects 0.000 claims description 9
- 238000000576 coating method Methods 0.000 claims description 8
- 230000035515 penetration Effects 0.000 claims description 8
- 230000002093 peripheral effect Effects 0.000 claims description 5
- 238000010030 laminating Methods 0.000 claims description 4
- 229910052709 silver Inorganic materials 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 2
- 229910052737 gold Inorganic materials 0.000 claims description 2
- 239000004020 conductor Substances 0.000 description 49
- 239000011810 insulating material Substances 0.000 description 28
- 238000009413 insulation Methods 0.000 description 14
- 239000000463 material Substances 0.000 description 14
- 206010040844 Skin exfoliation Diseases 0.000 description 11
- 230000006355 external stress Effects 0.000 description 9
- 239000010408 film Substances 0.000 description 8
- 239000011230 binding agent Substances 0.000 description 7
- 230000007547 defect Effects 0.000 description 7
- 238000007599 discharging Methods 0.000 description 5
- 230000007423 decrease Effects 0.000 description 3
- 238000009713 electroplating Methods 0.000 description 3
- 239000010409 thin film Substances 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 2
- 230000007797 corrosion Effects 0.000 description 2
- 238000005260 corrosion Methods 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 2
- 230000001788 irregular Effects 0.000 description 2
- 238000003475 lamination Methods 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 230000000149 penetrating effect Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000010292 electrical insulation Methods 0.000 description 1
- 239000013071 indirect material Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000005096 rolling process Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/0557—Disposition the external layer being disposed on a via connection of the semiconductor or solid-state body
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- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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- H01L2924/14—Integrated circuits
Description
また、昨今、半導体素子が完成した後に電極を裏面に取り出す方法として、Si基材は貫通しているが、半導体素子形成面に対する裏面側に電極の薄膜を残し、導電経路を形成する貫通電極構造が多くなっている。
図7において、1は基板、2は貫通孔、3はバインダーを添加した導体層、4はバインダーを含まない導体層である。
また、電解めっき法により導電層を形成する場合、貫通孔にスパッタ、蒸着法によりメッキ形成のための密着層、シード層を形成した後、ウェットプロセスにより電解メッキを施すため、工程が長く、また、液体に浸漬することによりイオン成分がデバイスに残り、リーク不良を発生する危険性がある。
(実施の形態1)
まず、実施の形態1における半導体貫通電極形成方法について、図1〜図3を用いて説明する。
まず、表面に形成された半導体素子の電極と裏面の電極PAD102とを導通させるために、電極PAD102の形成位置にSiデバイス101を貫通する貫通孔を形成した後、貫通孔の半導体素子形成面に対する裏面側に電極PAD102を形成し、その後、貫通孔の周辺部分に絶縁材料104、貫通孔の中央部分に導電性材料105を形成し、最後に導通材料105と半導体素子の電極とを電気的に接続することにより、基板表面の半導体素子の電極を基板裏面の電極PAD102に引き出す貫通電極が形成される。
また、絶縁性樹脂を円周状に形成する際に、図1,図2に示すように複数のインクジェット吐出樹脂により径方向の厚みを形成しても良いし、1つのインクジェット吐出樹脂の幅が厚みになるように吐出量を調整しても良い。同様に、導電性樹脂に関しても、1つのインクジェット吐出樹脂で一層分の導電性樹脂を形成しても良いし、複数のインクジェット吐出樹脂で一層分の導電性樹脂を形成しても良い。
図4は実施の形態2における貫通電極の構成を示す断面図である。
図4において、図1および図2と同じ構成要素については同じ符号を用い、説明を省略する。
(実施の形態3)
図5は実施の形態3における貫通電極の構成を示す断面図であり、図5(a)は導電性材料の径が貫通孔中央部で大きくなる構成を示す図、図5(b)は導電性材料の径が交互に大きくなる構成を示す図である。
図5(a)に示すように、実施の形態3における貫通電極では、実施の形態2とは逆に、絶縁材料104を貫通電極の深さ方向における中央部での幅が細くなるように充填し、それに対応して、導電性材料105を貫通電極の深さ方向における中央部で径が太くなるように充填する。
(実施の形態4)
図6は実施の形態4における貫通電極の構成を示す断面図である。
図6に示すように、実施の形態1〜実施の形態3の構成に加えて、実施の形態4における貫通電極では、貫通電極を電極PAD102方向に向かって細くなるようなテーパー状に形成し、導電性材料105が貫通電極の径に応じて、電極PAD102方向に向かって径が小さくなるように充填される。
2 貫通孔
3 バインダーを添加した導体層
4 バインダーを含まない導体層
101 Siデバイス
102 電極PAD
103 Si酸化膜
104 絶縁材料
105 導電性材料
106 インクジェット吐出樹脂
Claims (7)
- 基板表面に形成された半導体素子の電極と基板裏面に形成された電極PADを電気的に接続する半導体貫通電極の形成方法であって、
前記電極PAD上の前記基板に貫通孔を形成する工程と、
前記基板表面から前記貫通孔の内周に沿ってインクジェット塗布方法により表面に凹凸を有する不規則な形状の絶縁樹脂ペーストを中央部に空間を備えるように1層形成する絶縁樹脂形成工程と、
前記基板表面から前記空間内にインクジェット塗布方法により表面に凹凸を有する不規則な形状の1または複数の導電性樹脂ペーストを1層充填する導電性樹脂充填工程と、
前記貫通孔の基板表面まで前記絶縁樹脂ペーストおよび前記導電性樹脂ペーストが充填されるまで前記絶縁樹脂形成工程および前記導電性樹脂充填工程を順に繰り返す積層工程と
を備え、前記積層工程の際に、前記絶縁樹脂形成工程での前記絶縁樹脂の前記貫通孔の径方向に対する厚さを交互に大小させることを特徴とする半導体貫通電極形成方法。 - 前記絶縁樹脂形成工程で、前記貫通孔の深さ方向に対する中央部近郊に形成される絶縁樹脂の前記貫通孔の径方向に対する厚さを周辺部の厚さより大きくすることを特徴とする請求項1記載の半導体貫通電極形成方法。
- 前記絶縁樹脂形成工程で、前記貫通孔の深さ方向に対する中央部近郊に形成される絶縁樹脂の前記貫通孔の径方向に対する厚さを周辺部の厚さより小さくすることを特徴とする請求項1記載の半導体貫通電極形成方法。
- 前記貫通孔の径方向に対する大きさが、前記基板表面側から前記基板裏面側に向けて連続的に小さくなるように前記貫通孔を形成することを特徴とする請求項1〜請求項3のいずれかに記載の半導体貫通電極形成方法。
- 前記導電性樹脂ペ−ストがAuまたはCuまたはAgであることを特徴とする請求項1〜請求項4のいずれかに記載の半導体貫通電極形成方法。
- 前記絶縁樹脂ペーストおよび前記導電性樹脂ペーストの塗布の際に、層毎に塗布位置をずらすことを特徴とする請求項1〜請求項5のいずれかに記載の半導体貫通電極形成方法。
- 前記絶縁樹脂ペーストおよび前記導電性樹脂ペーストの塗布の際に、層毎に塗布量を変化させることを特徴とする請求項1〜請求項6のいずれかに記載の半導体貫通電極形成方法。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
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JP2008124122A JP5219612B2 (ja) | 2008-05-12 | 2008-05-12 | 半導体貫通電極形成方法 |
CN2009101332677A CN101582384B (zh) | 2008-05-12 | 2009-03-31 | 半导体贯通电极形成方法 |
US12/432,185 US7955974B2 (en) | 2008-05-12 | 2009-04-29 | Formation of a through-electrode by inkjet deposition of resin pastes |
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JP2008124122A JP5219612B2 (ja) | 2008-05-12 | 2008-05-12 | 半導体貫通電極形成方法 |
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JP2009272575A JP2009272575A (ja) | 2009-11-19 |
JP5219612B2 true JP5219612B2 (ja) | 2013-06-26 |
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JP5676941B2 (ja) * | 2010-07-06 | 2015-02-25 | キヤノン株式会社 | 配線基板の製造方法及び配線基板 |
CN104347548A (zh) * | 2013-08-02 | 2015-02-11 | 中芯国际集成电路制造(上海)有限公司 | 一种半导体器件及其制造方法 |
EP2844044A1 (de) * | 2013-09-03 | 2015-03-04 | Mass GmbH | Anlage und Verfahren zum Füllen von Löchern in einer Leiterplatte |
US9373605B1 (en) * | 2015-07-16 | 2016-06-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | DIE packages and methods of manufacture thereof |
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JP4741045B2 (ja) * | 1998-03-25 | 2011-08-03 | セイコーエプソン株式会社 | 電気回路、その製造方法および電気回路製造装置 |
JP3879816B2 (ja) * | 2000-06-02 | 2007-02-14 | セイコーエプソン株式会社 | 半導体装置及びその製造方法、積層型半導体装置、回路基板並びに電子機器 |
JP4498715B2 (ja) * | 2003-09-26 | 2010-07-07 | 株式会社半導体エネルギー研究所 | 半導体装置の作製方法 |
JPWO2006070652A1 (ja) * | 2004-12-27 | 2008-06-12 | 日本電気株式会社 | 半導体装置およびその製造方法と、配線基板およびその製造方法と、半導体パッケージ並びに電子機器 |
JP2006269968A (ja) * | 2005-03-25 | 2006-10-05 | Sharp Corp | 半導体装置およびその製造方法 |
KR100777021B1 (ko) * | 2006-07-31 | 2007-11-16 | 한국생산기술연구원 | 미세 비아홀 형성 방법 및 이 비아홀 형성방법을 이용한다층 인쇄회로기판 |
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US20090280647A1 (en) | 2009-11-12 |
CN101582384B (zh) | 2011-06-22 |
JP2009272575A (ja) | 2009-11-19 |
US7955974B2 (en) | 2011-06-07 |
CN101582384A (zh) | 2009-11-18 |
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