JP5214525B2 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
JP5214525B2
JP5214525B2 JP2009102270A JP2009102270A JP5214525B2 JP 5214525 B2 JP5214525 B2 JP 5214525B2 JP 2009102270 A JP2009102270 A JP 2009102270A JP 2009102270 A JP2009102270 A JP 2009102270A JP 5214525 B2 JP5214525 B2 JP 5214525B2
Authority
JP
Japan
Prior art keywords
circuit
inductor
wiring
connection terminal
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2009102270A
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English (en)
Japanese (ja)
Other versions
JP2010251662A (ja
JP2010251662A5 (https=
Inventor
康隆 中柴
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Electronics Corp
Original Assignee
Renesas Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Electronics Corp filed Critical Renesas Electronics Corp
Priority to JP2009102270A priority Critical patent/JP5214525B2/ja
Priority to US12/761,628 priority patent/US8283752B2/en
Publication of JP2010251662A publication Critical patent/JP2010251662A/ja
Publication of JP2010251662A5 publication Critical patent/JP2010251662A5/ja
Priority to US13/610,543 priority patent/US8692354B2/en
Application granted granted Critical
Publication of JP5214525B2 publication Critical patent/JP5214525B2/ja
Priority to US14/176,193 priority patent/US8896095B2/en
Priority to US14/518,024 priority patent/US9355998B2/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/43—Layouts of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/497—Inductive arrangements or effects of, or between, wiring layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/293—Configurations of stacked chips characterised by non-galvanic coupling between the chips, e.g. capacitive coupling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F17/00—Fixed inductances of the signal type
    • H01F17/0006—Printed inductances
    • H01F17/0013—Printed inductances with stacked layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F38/00—Adaptations of transformers or inductances for specific applications or functions
    • H01F38/14—Inductive couplings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/29—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/922—Bond pads being integral with underlying chip-level interconnections
    • H10W72/9226—Bond pads being integral with underlying chip-level interconnections with via interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/923—Bond pads having multiple stacked layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/9415—Dispositions of bond pads relative to the surface, e.g. recessed, protruding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/942—Dispositions of bond pads relative to underlying supporting features, e.g. bond pads, RDLs or vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/728—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked discrete passive device, e.g. resistors, capacitors or inductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Physics & Mathematics (AREA)
  • Geometry (AREA)
JP2009102270A 2009-04-20 2009-04-20 半導体装置 Expired - Fee Related JP5214525B2 (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP2009102270A JP5214525B2 (ja) 2009-04-20 2009-04-20 半導体装置
US12/761,628 US8283752B2 (en) 2009-04-20 2010-04-16 Semiconductor device
US13/610,543 US8692354B2 (en) 2009-04-20 2012-09-11 Semiconductor device
US14/176,193 US8896095B2 (en) 2009-04-20 2014-02-10 Semiconductor device with circuits connected to each other in contactless manner
US14/518,024 US9355998B2 (en) 2009-04-20 2014-10-20 Semiconductor device with circuits connected to each other in contactless manner

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2009102270A JP5214525B2 (ja) 2009-04-20 2009-04-20 半導体装置

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2013036724A Division JP5562459B2 (ja) 2013-02-27 2013-02-27 半導体装置

Publications (3)

Publication Number Publication Date
JP2010251662A JP2010251662A (ja) 2010-11-04
JP2010251662A5 JP2010251662A5 (https=) 2012-06-07
JP5214525B2 true JP5214525B2 (ja) 2013-06-19

Family

ID=42980573

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009102270A Expired - Fee Related JP5214525B2 (ja) 2009-04-20 2009-04-20 半導体装置

Country Status (2)

Country Link
US (4) US8283752B2 (https=)
JP (1) JP5214525B2 (https=)

Cited By (1)

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US8696879B2 (en) 2007-09-14 2014-04-15 Cardinal Cg Company Low-maintenance coating technology

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JP5578797B2 (ja) * 2009-03-13 2014-08-27 ルネサスエレクトロニクス株式会社 半導体装置
JP5214525B2 (ja) * 2009-04-20 2013-06-19 ルネサスエレクトロニクス株式会社 半導体装置
US20120062040A1 (en) * 2009-06-04 2012-03-15 Shunichi Kaeriyama Semiconductor device and signal transmission method
US8569861B2 (en) 2010-12-22 2013-10-29 Analog Devices, Inc. Vertically integrated systems
IT1404038B1 (it) * 2010-12-29 2013-11-08 St Microelectronics Srl Dispositivo elettronico a semiconduttore provvisto di un elemento isolatore galvanico integrato, e relativo procedimento di assemblaggio
US8890319B2 (en) * 2012-09-12 2014-11-18 Infineon Technologies Ag Chip to package interface
JP5661707B2 (ja) * 2012-09-18 2015-01-28 ウィン セミコンダクターズ コーポレーション 化合物半導体集積回路
JP6127570B2 (ja) * 2013-02-20 2017-05-17 セイコーエプソン株式会社 半導体装置及び電子機器
CN105051886B (zh) * 2013-03-25 2018-06-08 瑞萨电子株式会社 半导体装置及其制造方法
JP6182985B2 (ja) 2013-06-05 2017-08-23 セイコーエプソン株式会社 電気光学装置、電気光学装置の製造方法、電子機器
US9165791B2 (en) 2013-10-31 2015-10-20 Qualcomm Incorporated Wireless interconnects in an interposer
JP6395304B2 (ja) * 2013-11-13 2018-09-26 ローム株式会社 半導体装置および半導体モジュール
US9209131B2 (en) 2014-01-21 2015-12-08 Qualcomm Incorporated Toroid inductor in redistribution layers (RDL) of an integrated device
JP6249960B2 (ja) * 2014-01-29 2017-12-20 ルネサスエレクトロニクス株式会社 半導体装置
US9425143B2 (en) 2014-11-17 2016-08-23 Qualcomm Incorporated Integrated device package comprising an electromagnetic (EM) passive device in an encapsulation layer, and an EM shield
JP6449439B2 (ja) 2015-03-30 2019-01-09 株式会社ＰＥＺＹ Ｃｏｍｐｕｔｉｎｇ 半導体装置
US10720788B2 (en) * 2015-10-09 2020-07-21 Taiwan Semiconductor Manufacturing Company, Ltd. Wireless charging devices having wireless charging coils and methods of manufacture thereof
JP6764252B2 (ja) * 2016-05-10 2020-09-30 ローム株式会社 電子部品およびその製造方法
JP6619698B2 (ja) * 2016-06-09 2019-12-11 ルネサスエレクトロニクス株式会社 半導体装置、及び通信回路
US10249580B2 (en) * 2016-06-22 2019-04-02 Qualcomm Incorporated Stacked substrate inductor
US10446508B2 (en) * 2016-09-01 2019-10-15 Mediatek Inc. Semiconductor package integrated with memory die
US12117415B2 (en) 2017-05-15 2024-10-15 Analog Devices International Unlimited Company Integrated ion sensing apparatus and methods
US11276663B2 (en) * 2017-05-19 2022-03-15 Shindengen Electric Manufacturing Co., Ltd. Electronic module
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JP2018186280A (ja) * 2018-06-25 2018-11-22 ルネサスエレクトロニクス株式会社 半導体装置
JP7101627B2 (ja) * 2019-01-29 2022-07-15 ルネサスエレクトロニクス株式会社 半導体モジュールおよびその製造方法
JP7232137B2 (ja) * 2019-06-25 2023-03-02 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
US11587839B2 (en) 2019-06-27 2023-02-21 Analog Devices, Inc. Device with chemical reaction chamber
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JP2021082786A (ja) * 2019-11-22 2021-05-27 ルネサスエレクトロニクス株式会社 半導体装置
JP2021174955A (ja) * 2020-04-30 2021-11-01 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
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WO2025084215A1 (ja) * 2023-10-19 2025-04-24 株式会社Premo 半導体装置、および半導体チップ

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8696879B2 (en) 2007-09-14 2014-04-15 Cardinal Cg Company Low-maintenance coating technology

Also Published As

Publication number Publication date
JP2010251662A (ja) 2010-11-04
US8896095B2 (en) 2014-11-25
US9355998B2 (en) 2016-05-31
US20140151904A1 (en) 2014-06-05
US20130001742A1 (en) 2013-01-03
US20150035116A1 (en) 2015-02-05
US8692354B2 (en) 2014-04-08
US20100265024A1 (en) 2010-10-21
US8283752B2 (en) 2012-10-09

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