JP5207336B2 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
JP5207336B2
JP5207336B2 JP2006155658A JP2006155658A JP5207336B2 JP 5207336 B2 JP5207336 B2 JP 5207336B2 JP 2006155658 A JP2006155658 A JP 2006155658A JP 2006155658 A JP2006155658 A JP 2006155658A JP 5207336 B2 JP5207336 B2 JP 5207336B2
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Prior art keywords
semiconductor chip
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electrode pads
chip
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Expired - Fee Related
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JP2006155658A
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English (en)
Japanese (ja)
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JP2007324506A (ja
JP2007324506A5 (enExample
Inventor
宏 黒田
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Renesas Electronics Corp
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Renesas Electronics Corp
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Priority to JP2006155658A priority Critical patent/JP5207336B2/ja
Priority to US11/756,941 priority patent/US7777347B2/en
Publication of JP2007324506A publication Critical patent/JP2007324506A/ja
Publication of JP2007324506A5 publication Critical patent/JP2007324506A5/ja
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    • H—ELECTRICITY
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    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)
JP2006155658A 2006-06-05 2006-06-05 半導体装置 Expired - Fee Related JP5207336B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2006155658A JP5207336B2 (ja) 2006-06-05 2006-06-05 半導体装置
US11/756,941 US7777347B2 (en) 2006-06-05 2007-06-01 Semiconductor device

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Application Number Priority Date Filing Date Title
JP2006155658A JP5207336B2 (ja) 2006-06-05 2006-06-05 半導体装置

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JP2007324506A JP2007324506A (ja) 2007-12-13
JP2007324506A5 JP2007324506A5 (enExample) 2009-07-09
JP5207336B2 true JP5207336B2 (ja) 2013-06-12

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WO2008131058A2 (en) * 2007-04-17 2008-10-30 Rambus Inc. Hybrid volatile and non-volatile memory device
JP5183186B2 (ja) * 2007-12-14 2013-04-17 ルネサスエレクトロニクス株式会社 半導体装置
KR20130007602A (ko) * 2010-03-18 2013-01-18 모사이드 테크놀로지스 인코퍼레이티드 오프셋 다이 스태킹의 멀티-칩 패키지 및 그 제조 방법
JP2017078958A (ja) * 2015-10-20 2017-04-27 株式会社東芝 半導体装置
US11195820B2 (en) * 2020-03-03 2021-12-07 Sandisk Technologies Llc Semiconductor device including fractured semiconductor dies

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Publication number Priority date Publication date Assignee Title
JP3545200B2 (ja) * 1997-04-17 2004-07-21 シャープ株式会社 半導体装置
DE10142120A1 (de) * 2001-08-30 2003-03-27 Infineon Technologies Ag Elektronisches Bauteil mit wenigstens zwei gestapelten Halbleiterchips sowie Verfahren zu seiner Herstellung
JP4076841B2 (ja) * 2002-11-07 2008-04-16 シャープ株式会社 半導体装置の製造方法
JP4068974B2 (ja) * 2003-01-22 2008-03-26 株式会社ルネサステクノロジ 半導体装置
KR100621547B1 (ko) * 2004-01-13 2006-09-14 삼성전자주식회사 멀티칩 패키지
US7378725B2 (en) * 2004-03-31 2008-05-27 Intel Corporation Semiconducting device with stacked dice
JP2005322767A (ja) 2004-05-10 2005-11-17 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法
JP4188337B2 (ja) * 2004-05-20 2008-11-26 株式会社東芝 積層型電子部品の製造方法
JP4215689B2 (ja) * 2004-06-17 2009-01-28 株式会社新川 ワイヤボンディング方法及びバンプ形成方法
JP2006066816A (ja) * 2004-08-30 2006-03-09 Toshiba Corp 半導体装置の製造方法及び半導体装置
US20070001296A1 (en) * 2005-05-31 2007-01-04 Stats Chippac Ltd. Bump for overhang device
US7229928B2 (en) * 2005-08-31 2007-06-12 Infineon Technologies Ag Method for processing a layered stack in the production of a semiconductor device

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US7777347B2 (en) 2010-08-17
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