JP2005322767A - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
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- JP2005322767A JP2005322767A JP2004139502A JP2004139502A JP2005322767A JP 2005322767 A JP2005322767 A JP 2005322767A JP 2004139502 A JP2004139502 A JP 2004139502A JP 2004139502 A JP2004139502 A JP 2004139502A JP 2005322767 A JP2005322767 A JP 2005322767A
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- lower chip
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- semiconductor device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
Landscapes
- Wire Bonding (AREA)
Abstract
【解決手段】 配線基板1と、配線基板上に実装された下側チップ3と、下側チップ上に取り付けられたスペーサ5aと、スペーサ上に実装された、下側チップより寸法が大きい上側チップ6とを備え、スペーサは、下側チップの周囲に延出して上側チップの周縁部に配置される部分を有する。スペーサが一つであり、上側チップのスペーサへの実装において、上側チップの中央部および周縁部にも接合する領域を確保することができる。このことにより、上側チップのボンディングパッドと配線基板上の端子を金属細線で接続する際に、上側チップの撓みがなく超音波の伝達をより安定させることができる。
【選択図】 図1
Description
2 接着剤
3 下側チップ
4 金属細線
5a,5b,5c,5d スペーサ
6 上側チップ
7 樹脂
8 半田ボール
10 中央部
11 外周部
12 連結部
13 円柱形状部
14 中央部
15 延出部
16 四角柱部
17 平板部
Claims (7)
- 配線基板と、前記配線基板上に実装された下側チップと、前記下側チップ上に取り付けられたスペーサと、前記スペーサ上に実装された、前記下側チップより寸法が大きい上側チップとを備え、前記スペーサは、前記下側チップの周囲に延出して前記上側チップの周縁部に配置される部分を有することを特徴とする半導体装置。
- 前記スペーサが、前記下側チップおよび前記上側チップと接合される中央部と、前記中央部の外周に配置されて前記上側チップと接合される外周部とを有し、前記中央部と前記外周部は外形が四角形であり、かつ4コーナで連結した形状である請求項1記載の半導体装置。
- 前記スペーサの外周部の4コーナに、配線基板と接合される支持部を有する請求項2記載の半導体装置。
- 前記スペーサが、前記下側チップおよび前記上側チップと接合される外形が四角形の中央部を有し、前記中央部の4コーナを外方向へ延出した形状である請求項1記載の半導体装置。
- 前記スペーサの中央部のコーナを外方向へ延出した端部に、配線基板と接合される支持部を有する請求項4記載の半導体装置。
- 前記スペーサが、前記下側チップと接合される四角柱部と、前記上側チップと接合される前記四角柱部より大きい平板部とを一体に形成した凸型形状である請求項1記載の半導体装置。
- 配線基板上に下側チップを実装する工程と、前記配線基板が有する端子と前記下側チップが有するボンディングパッドを金属細線により接続する工程と、前記下側チップ上に下側チップの周囲に延出した部分を有するスペーサを取り付ける工程と、前記スペーサ上に前記下側チップより寸法が大きい上側チップを実装する工程と、前記配線基板が有する端子と前記上側チップが有するボンディングパッドを金属細線により接続する工程と、前記配線基板上の前記下側チップ、スペーサ、上側チップおよび金属細線を樹脂により封止する工程とを含む半導体装置の製造方法。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004139502A JP2005322767A (ja) | 2004-05-10 | 2004-05-10 | 半導体装置およびその製造方法 |
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JP2004139502A JP2005322767A (ja) | 2004-05-10 | 2004-05-10 | 半導体装置およびその製造方法 |
Publications (1)
Publication Number | Publication Date |
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JP2005322767A true JP2005322767A (ja) | 2005-11-17 |
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JP2004139502A Pending JP2005322767A (ja) | 2004-05-10 | 2004-05-10 | 半導体装置およびその製造方法 |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7777347B2 (en) | 2006-06-05 | 2010-08-17 | Renesas Technology Corp. | Semiconductor device |
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2004
- 2004-05-10 JP JP2004139502A patent/JP2005322767A/ja active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7777347B2 (en) | 2006-06-05 | 2010-08-17 | Renesas Technology Corp. | Semiconductor device |
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