JP5198573B2 - クロスポイント型抵抗変化メモリ - Google Patents
クロスポイント型抵抗変化メモリ Download PDFInfo
- Publication number
- JP5198573B2 JP5198573B2 JP2010532742A JP2010532742A JP5198573B2 JP 5198573 B2 JP5198573 B2 JP 5198573B2 JP 2010532742 A JP2010532742 A JP 2010532742A JP 2010532742 A JP2010532742 A JP 2010532742A JP 5198573 B2 JP5198573 B2 JP 5198573B2
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- voltage pulse
- lines
- column lines
- resistance change
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0069—Writing or programming circuits or methods
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0007—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising metal oxide memory material, e.g. perovskites
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0023—Address circuits or decoders
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0033—Disturbance prevention or evaluation; Refreshing of disturbed memory data
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0069—Writing or programming circuits or methods
- G11C2013/0092—Write characterized by the shape, e.g. form, length, amplitude of the write pulse
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
- G11C2213/70—Resistive array aspects
- G11C2213/71—Three dimensional array
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
- G11C2213/70—Resistive array aspects
- G11C2213/72—Array wherein the access device being a diode
Landscapes
- Chemical & Material Sciences (AREA)
- Engineering & Computer Science (AREA)
- Materials Engineering (AREA)
- Crystallography & Structural Chemistry (AREA)
- Semiconductor Memories (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/JP2008/068395 WO2010041325A1 (ja) | 2008-10-09 | 2008-10-09 | クロスポイント型抵抗変化メモリ |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPWO2010041325A1 JPWO2010041325A1 (ja) | 2012-03-01 |
| JP5198573B2 true JP5198573B2 (ja) | 2013-05-15 |
Family
ID=42100290
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2010532742A Expired - Fee Related JP5198573B2 (ja) | 2008-10-09 | 2008-10-09 | クロスポイント型抵抗変化メモリ |
Country Status (4)
| Country | Link |
|---|---|
| US (2) | US8498142B2 (enExample) |
| JP (1) | JP5198573B2 (enExample) |
| TW (2) | TWI413120B (enExample) |
| WO (1) | WO2010041325A1 (enExample) |
Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010009669A (ja) | 2008-06-26 | 2010-01-14 | Toshiba Corp | 半導体記憶装置 |
| US9177639B1 (en) * | 2010-12-09 | 2015-11-03 | Adesto Technologies Corporation | Memory devices, circuits and methods having data values based on dynamic change in material property |
| JP5562890B2 (ja) * | 2011-03-30 | 2014-07-30 | 株式会社東芝 | 抵抗変化メモリ |
| US8837205B2 (en) * | 2012-05-30 | 2014-09-16 | Freescale Semiconductor, Inc. | Multi-port register file with multiplexed data |
| US9165649B2 (en) * | 2013-12-20 | 2015-10-20 | Sandisk Technologies Inc. | Systems and methods of shaping data |
| US10706927B1 (en) * | 2018-05-08 | 2020-07-07 | SK Hynix Inc. | Electronic device and operating method thereof |
| JP2020155192A (ja) | 2019-03-22 | 2020-09-24 | キオクシア株式会社 | メモリデバイス |
| US12283319B2 (en) * | 2019-08-02 | 2025-04-22 | Peking University | Operating circuit and operating method of resistive random access memory |
| JP2021047969A (ja) | 2019-09-20 | 2021-03-25 | キオクシア株式会社 | メモリデバイス |
| JP7150787B2 (ja) * | 2020-07-31 | 2022-10-11 | ウィンボンド エレクトロニクス コーポレーション | 抵抗変化型クロスバーアレイ装置 |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005522045A (ja) * | 2002-04-04 | 2005-07-21 | 株式会社東芝 | 相変化メモリ装置 |
| WO2008035392A1 (en) * | 2006-09-19 | 2008-03-27 | Renesas Technology Corp. | Semiconductor integrated circuit device |
| JP2008123595A (ja) * | 2006-11-10 | 2008-05-29 | Matsushita Electric Ind Co Ltd | 半導体記憶装置 |
Family Cites Families (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030218905A1 (en) * | 2002-05-22 | 2003-11-27 | Perner Frederick A. | Equi-potential sensing magnetic random access memory (MRAM) with series diodes |
| US7394680B2 (en) * | 2003-03-18 | 2008-07-01 | Kabushiki Kaisha Toshiba | Resistance change memory device having a variable resistance element with a recording layer electrode served as a cation source in a write or erase mode |
| EP1609154B1 (en) * | 2003-03-18 | 2013-12-25 | Kabushiki Kaisha Toshiba | Phase change memory device |
| KR100564577B1 (ko) * | 2003-09-25 | 2006-03-28 | 삼성전자주식회사 | 리셋 상태에서 균일한 저항 범위를 가지는 상 변화 메모리장치 및 방법 |
| US7082052B2 (en) * | 2004-02-06 | 2006-07-25 | Unity Semiconductor Corporation | Multi-resistive state element with reactive metal |
| US7042757B2 (en) * | 2004-03-04 | 2006-05-09 | Hewlett-Packard Development Company, L.P. | 1R1D MRAM block architecture |
| US7499306B2 (en) * | 2004-09-11 | 2009-03-03 | Samsung Electronics Co., Ltd. | Phase-change memory device and method that maintains the resistance of a phase-change material in a set state within a constant resistance range |
| US7099180B1 (en) * | 2005-02-15 | 2006-08-29 | Intel Corporation | Phase change memory bits reset through a series of pulses of increasing amplitude |
| US7495944B2 (en) * | 2005-03-30 | 2009-02-24 | Ovonyx, Inc. | Reading phase change memories |
| JP4987386B2 (ja) * | 2006-08-16 | 2012-07-25 | 株式会社東芝 | 抵抗変化素子を有する半導体メモリ |
| US7505330B2 (en) * | 2006-08-31 | 2009-03-17 | Micron Technology, Inc. | Phase-change random access memory employing read before write for resistance stabilization |
| US7535756B2 (en) * | 2007-01-31 | 2009-05-19 | Macronix International Co., Ltd. | Method to tighten set distribution for PCRAM |
| JP2010009669A (ja) | 2008-06-26 | 2010-01-14 | Toshiba Corp | 半導体記憶装置 |
-
2008
- 2008-10-09 WO PCT/JP2008/068395 patent/WO2010041325A1/ja not_active Ceased
- 2008-10-09 JP JP2010532742A patent/JP5198573B2/ja not_active Expired - Fee Related
-
2009
- 2009-10-09 TW TW098134428A patent/TWI413120B/zh not_active IP Right Cessation
- 2009-10-09 TW TW102126508A patent/TW201403598A/zh not_active IP Right Cessation
-
2011
- 2011-03-25 US US13/072,029 patent/US8498142B2/en not_active Expired - Fee Related
-
2013
- 2013-07-09 US US13/937,274 patent/US8681532B2/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005522045A (ja) * | 2002-04-04 | 2005-07-21 | 株式会社東芝 | 相変化メモリ装置 |
| WO2008035392A1 (en) * | 2006-09-19 | 2008-03-27 | Renesas Technology Corp. | Semiconductor integrated circuit device |
| JP2008123595A (ja) * | 2006-11-10 | 2008-05-29 | Matsushita Electric Ind Co Ltd | 半導体記憶装置 |
Also Published As
| Publication number | Publication date |
|---|---|
| TW201403598A (zh) | 2014-01-16 |
| US20110228590A1 (en) | 2011-09-22 |
| TWI563501B (enExample) | 2016-12-21 |
| TWI413120B (zh) | 2013-10-21 |
| TW201027529A (en) | 2010-07-16 |
| US8498142B2 (en) | 2013-07-30 |
| US8681532B2 (en) | 2014-03-25 |
| JPWO2010041325A1 (ja) | 2012-03-01 |
| US20130294147A1 (en) | 2013-11-07 |
| WO2010041325A1 (ja) | 2010-04-15 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| TRDD | Decision of grant or rejection written | ||
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20130115 |
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| A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20130206 |
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| LAPS | Cancellation because of no payment of annual fees |