JP5190205B2 - 半導体素子の製造方法 - Google Patents
半導体素子の製造方法 Download PDFInfo
- Publication number
- JP5190205B2 JP5190205B2 JP2007027870A JP2007027870A JP5190205B2 JP 5190205 B2 JP5190205 B2 JP 5190205B2 JP 2007027870 A JP2007027870 A JP 2007027870A JP 2007027870 A JP2007027870 A JP 2007027870A JP 5190205 B2 JP5190205 B2 JP 5190205B2
- Authority
- JP
- Japan
- Prior art keywords
- contact
- film
- contact hole
- contact holes
- axis direction
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
- H10W20/42—Vias, e.g. via plugs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/01—Manufacture or treatment
- H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/071—Manufacture or treatment of dielectric parts thereof
- H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
- H10W20/082—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts the openings being tapered via holes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/071—Manufacture or treatment of dielectric parts thereof
- H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
- H10W20/089—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
- H10B12/318—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor the storage electrode having multiple segments
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Memories (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020060011569A KR100809324B1 (ko) | 2006-02-07 | 2006-02-07 | 반도체 소자 및 그 제조 방법 |
| KR10-2006-0011569 | 2006-02-07 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2007214567A JP2007214567A (ja) | 2007-08-23 |
| JP2007214567A5 JP2007214567A5 (https=) | 2010-03-25 |
| JP5190205B2 true JP5190205B2 (ja) | 2013-04-24 |
Family
ID=38333213
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2007027870A Expired - Fee Related JP5190205B2 (ja) | 2006-02-07 | 2007-02-07 | 半導体素子の製造方法 |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US7622759B2 (https=) |
| JP (1) | JP5190205B2 (https=) |
| KR (1) | KR100809324B1 (https=) |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090302479A1 (en) * | 2008-06-06 | 2009-12-10 | Avago Technologies Wireless Ip (Singapore) Pte. Ltd. | Semiconductor structures having vias |
| KR101094380B1 (ko) * | 2008-12-29 | 2011-12-15 | 주식회사 하이닉스반도체 | 금속콘택을 갖는 반도체장치 제조 방법 |
| JP4945619B2 (ja) | 2009-09-24 | 2012-06-06 | 株式会社東芝 | 半導体記憶装置 |
| KR101123804B1 (ko) * | 2009-11-20 | 2012-03-12 | 주식회사 하이닉스반도체 | 반도체 칩 및 이를 갖는 적층 반도체 패키지 |
| KR101824735B1 (ko) * | 2010-12-15 | 2018-02-01 | 에스케이하이닉스 주식회사 | 반도체 소자의 제조 방법 |
| TWI447858B (zh) * | 2012-02-03 | 2014-08-01 | Inotera Memories Inc | 隨機存取記憶體的製造方法 |
| US8759977B2 (en) | 2012-04-30 | 2014-06-24 | International Business Machines Corporation | Elongated via structures |
| US9324573B2 (en) | 2013-01-24 | 2016-04-26 | Ps5 Luxco S.A.R.L. | Method for manufacturing semiconductor device |
| JP2015053337A (ja) | 2013-09-05 | 2015-03-19 | マイクロン テクノロジー, インク. | 半導体装置及びその製造方法 |
Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR970000384B1 (ko) | 1994-01-10 | 1997-01-09 | 삼영전자공업 주식회사 | 키틴 및 키토산계 액상복합비료 |
| KR970003848A (ko) * | 1995-06-28 | 1997-01-29 | 김주용 | 반도체 소자의 콘택 제조방법 |
| KR100291414B1 (ko) * | 1998-05-04 | 2001-07-12 | 김영환 | 반도체장치의캐패시터및그제조방법 |
| KR100307528B1 (ko) | 1998-05-28 | 2001-11-02 | 김영환 | 반도체소자의다층배선구조제조방법 |
| KR20010059181A (ko) | 1999-12-30 | 2001-07-06 | 박종섭 | 반도체 소자의 콘택 플러그 형성방법 |
| KR20010095943A (ko) * | 2000-04-14 | 2001-11-07 | 윤종용 | 반도체 장치 |
| JP4223189B2 (ja) * | 2000-12-26 | 2009-02-12 | 富士通マイクロエレクトロニクス株式会社 | 半導体装置及びその製造方法 |
| JP3976703B2 (ja) | 2003-04-30 | 2007-09-19 | エルピーダメモリ株式会社 | 半導体装置の製造方法 |
| JP2006024831A (ja) * | 2004-07-09 | 2006-01-26 | Sony Corp | 半導体装置および半導体装置の製造方法 |
| JP2007103410A (ja) * | 2005-09-30 | 2007-04-19 | Elpida Memory Inc | 密集コンタクトホールを有する半導体デバイス |
-
2006
- 2006-02-07 KR KR1020060011569A patent/KR100809324B1/ko not_active Expired - Fee Related
-
2007
- 2007-02-05 US US11/702,210 patent/US7622759B2/en not_active Expired - Fee Related
- 2007-02-07 JP JP2007027870A patent/JP5190205B2/ja not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JP2007214567A (ja) | 2007-08-23 |
| KR20070080346A (ko) | 2007-08-10 |
| US7622759B2 (en) | 2009-11-24 |
| US20070182017A1 (en) | 2007-08-09 |
| KR100809324B1 (ko) | 2008-03-05 |
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