JP5185446B2 - Stt−mramのワードライン電圧制御 - Google Patents
Stt−mramのワードライン電圧制御 Download PDFInfo
- Publication number
- JP5185446B2 JP5185446B2 JP2011533439A JP2011533439A JP5185446B2 JP 5185446 B2 JP5185446 B2 JP 5185446B2 JP 2011533439 A JP2011533439 A JP 2011533439A JP 2011533439 A JP2011533439 A JP 2011533439A JP 5185446 B2 JP5185446 B2 JP 5185446B2
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- word line
- stt
- power supply
- transition
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 230000007704 transition Effects 0.000 claims description 32
- 238000002955 isolation Methods 0.000 claims description 14
- 238000000034 method Methods 0.000 claims description 14
- 238000012546 transfer Methods 0.000 claims description 13
- 238000000926 separation method Methods 0.000 claims description 4
- 230000005540 biological transmission Effects 0.000 claims description 3
- 230000003247 decreasing effect Effects 0.000 claims description 3
- 238000005086 pumping Methods 0.000 claims 2
- 230000015556 catabolic process Effects 0.000 description 9
- 230000006870 function Effects 0.000 description 9
- 238000010586 diagram Methods 0.000 description 7
- 230000006378 damage Effects 0.000 description 6
- 230000008859 change Effects 0.000 description 4
- 238000013461 design Methods 0.000 description 3
- 230000009471 action Effects 0.000 description 2
- 238000013459 approach Methods 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000005415 magnetization Effects 0.000 description 2
- 230000003213 activating effect Effects 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000001276 controlling effect Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/165—Auxiliary circuits
- G11C11/1653—Address circuits or decoders
- G11C11/1657—Word-line or row circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/165—Auxiliary circuits
- G11C11/1659—Cell access
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/165—Auxiliary circuits
- G11C11/1673—Reading or sensing circuits or methods
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/165—Auxiliary circuits
- G11C11/1675—Writing or programming circuits or methods
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Mram Or Spin Memory Techniques (AREA)
- Hall/Mr Elements (AREA)
Description
401 ビットセル
405 MTJ
410 ワードライントランジスタ
420 ビットライン
430 ワードライン
432 ワードラインドライバ
440 ソースライン
450 読み出し分離素子
470 感知増幅器
500 書き込みドライバ
502、504 書き込み分離素子
510、520、530 インバータ
600 グラフ
610 基準線
620 ワードライン電圧
702 レベル検出器
704 Vppチャージポンプ
Claims (20)
- ビットラインおよびソースラインに結合された、磁気トンネル接合(MTJ)およびワードライントランジスタを有するビットセルと、
前記ワードライントランジスタのゲートに結合されたワードラインドライバとを備え、
前記ワードラインドライバは、遷移電圧より低い電源電圧に対して前記電源電圧より高いワードライン電圧を供給するように、前記遷移電圧より高い電源電圧に対して前記電源電圧より低い電圧を供給するように構成されるスピン転移トルク磁気抵抗ランダムアクセスメモリ(STT-MRAM)。 - 前記ワードライン電圧は前記遷移電圧に達した後に限界電圧以下にクランプされる請求項1に記載のSTT-MRAM。
- 前記ワードライン電圧は前記遷移電圧に達した後に減少される請求項2に記載のSTT-MRAM。
- 前記遷移電圧は低Vdd領域と高Vdd領域の間の遷移を表す請求項1に記載のSTT-MRAM。
- 前記ビットセルに電気信号を供給して前記ビットセルで論理状態を記憶するように構成された書き込みドライバと、
前記ビットラインとソースラインの間に前記書き込みドライバと直列に結合された少なくとも1つの書き込み分離素子とをさらに備え、
前記書き込み分離素子は読み出し動作中に前記書き込みドライバを分離するように構成される請求項1に記載のSTT-MRAM。 - 前記書き込みドライバは、
データ入力部と前記ビットラインの間に直列に結合された第1および第2のインバータと、
前記データ入力部と前記ソースラインの間に直列に結合された第3のインバータとを備える請求項4に記載のSTT-MRAM。 - 前記ビットセルと感知増幅器の間に挿入された読み出し分離素子をさらに備え、前記読み出し分離素子は、書き込み動作中に前記感知増幅器を前記ビットラインから選択的に分離するように構成される請求項1に記載のSTT-MRAM。
- 前記読み出し分離素子は、スイッチ、伝送ゲート、またはマルチプレクサのうち少なくとも1つである請求項6に記載のSTT-MRAM。
- 前記電源電圧から前記ワードライン電圧を発生させるように構成された電圧ポンプ回路をさらに備える請求項1に記載のSTT-MRAM。
- 前記電源電圧から前記ワードライン電圧を発生させる前記電圧ポンプ回路を制御するように構成されたレベル検出器をさらに備える請求項9に記載のSTT-MRAM。
- スピン転移トルク磁気抵抗ランダムアクセスメモリ(STT-MRAM)における読み出し動作および書き込み動作の方法であって、
書き込み動作中に電源電圧が遷移電圧より低い場合に、ビットセルのワードライントランジスタのゲートに前記電源電圧より高い第1の電圧を印加する段階と、
書き込み動作中に前記電源電圧が遷移電圧より高い場合に、前記ワードライントランジスタに前記電源電圧より低い第2の電圧を印加する段階とを含む方法。 - 前記遷移電圧を超えたところで前記ワードライン電圧を限界電圧以下にクランプして前記第2の電圧を供給する段階をさらに含む請求項11に記載の方法。
- 前記遷移電圧に達した後に前記第2の電圧を減少させて前記第2の電圧を供給する段階をさらに含む請求項11に記載の方法。
- 前記遷移電圧は低Vdd領域と高Vdd領域の間の遷移を表す請求項11に記載の方法。
- チャージポンプ回路を使用して前記電源電圧をポンピングして前記第1の電圧を発生させる段階をさらに含む請求項11に記載の方法。
- 書き込み動作中に電源電圧が遷移電圧より低い場合に、ビットセルのワードライントランジスタのゲートに前記電源電圧より高い第1の電圧を印加する手段と、
書き込み動作中に前記電源電圧が遷移電圧より高い場合に、前記ワードライントランジスタに前記電源電圧より低い第2の電圧を印加する手段とを備えるスピン転移トルク磁気抵抗ランダムアクセスメモリ(STT-MRAM)。 - 前記遷移電圧に達した後に前記ワードライン電圧を限界電圧以下にクランプして前記第2の電圧を供給する手段をさらに備える請求項16に記載のSTT-MRAM。
- 前記遷移電圧に達した後に前記第2の電圧を減少させて前記第2の電圧を供給する手段をさらに備える請求項16に記載のSTT-MRAM。
- 前記遷移電圧は低Vdd領域と高Vdd領域の間の遷移を表す請求項16に記載のSTT-MRAM。
- チャージポンプ回路を使用して前記電源電圧をポンピングして前記第1の電圧を発生させる手段をさらに備える請求項16に記載のSTT-MRAM。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/265,044 | 2008-11-05 | ||
US12/265,044 US8107280B2 (en) | 2008-11-05 | 2008-11-05 | Word line voltage control in STT-MRAM |
PCT/US2009/063245 WO2010053970A1 (en) | 2008-11-05 | 2009-11-04 | Word line voltage control in stt-mram |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2012506602A JP2012506602A (ja) | 2012-03-15 |
JP5185446B2 true JP5185446B2 (ja) | 2013-04-17 |
Family
ID=41506459
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2011533439A Active JP5185446B2 (ja) | 2008-11-05 | 2009-11-04 | Stt−mramのワードライン電圧制御 |
Country Status (9)
Country | Link |
---|---|
US (1) | US8107280B2 (ja) |
EP (1) | EP2353164B1 (ja) |
JP (1) | JP5185446B2 (ja) |
KR (1) | KR101257339B1 (ja) |
CN (1) | CN102203870B (ja) |
BR (1) | BRPI0921432B1 (ja) |
ES (1) | ES2532396T3 (ja) |
TW (1) | TWI436360B (ja) |
WO (1) | WO2010053970A1 (ja) |
Families Citing this family (47)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9728240B2 (en) * | 2009-04-08 | 2017-08-08 | Avalanche Technology, Inc. | Pulse programming techniques for voltage-controlled magnetoresistive tunnel junction (MTJ) |
KR101312366B1 (ko) * | 2011-04-06 | 2013-09-26 | 에스케이하이닉스 주식회사 | 자기 메모리 장치를 위한 라이트 드라이버 회로 및 자기 메모리 장치 |
US8929132B2 (en) | 2011-11-17 | 2015-01-06 | Everspin Technologies, Inc. | Write driver circuit and method for writing to a spin-torque MRAM |
US9047965B2 (en) | 2011-12-20 | 2015-06-02 | Everspin Technologies, Inc. | Circuit and method for spin-torque MRAM bit line and source line voltage regulation |
US8710900B2 (en) * | 2012-03-22 | 2014-04-29 | Fairchild Semiconductor Corporation | Methods and apparatus for voltage selection for a MOSFET switch device |
WO2013154564A1 (en) * | 2012-04-12 | 2013-10-17 | Intel Corporation | Selector for low voltage embedded memory |
KR20130139066A (ko) * | 2012-06-12 | 2013-12-20 | 삼성전자주식회사 | 소스라인 전압 발생기를 포함하는 자기 저항 메모리 장치 |
US9672885B2 (en) | 2012-09-04 | 2017-06-06 | Qualcomm Incorporated | MRAM word line power control scheme |
US9443574B2 (en) | 2012-10-31 | 2016-09-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Memory architecture |
KR20140107948A (ko) | 2013-02-28 | 2014-09-05 | 에스케이하이닉스 주식회사 | 반도체 장치 및 이를 포함하는 프로세서와 시스템 |
US9691464B2 (en) * | 2013-03-15 | 2017-06-27 | Avalanche Technology, Inc. | Fast programming of magnetic random access memory (MRAM) |
US8792269B1 (en) * | 2013-03-15 | 2014-07-29 | Avalanche Technology, Inc. | Fast programming of magnetic random access memory (MRAM) |
US9298946B2 (en) | 2013-09-09 | 2016-03-29 | Qualcomm Incorporated | Physically unclonable function based on breakdown voltage of metal-insulator-metal device |
US10223026B2 (en) * | 2013-09-30 | 2019-03-05 | Vmware, Inc. | Consistent and efficient mirroring of nonvolatile memory state in virtualized environments where dirty bit of page table entries in non-volatile memory are not cleared until pages in non-volatile memory are remotely mirrored |
US10140212B2 (en) | 2013-09-30 | 2018-11-27 | Vmware, Inc. | Consistent and efficient mirroring of nonvolatile memory state in virtualized environments by remote mirroring memory addresses of nonvolatile memory to which cached lines of the nonvolatile memory have been flushed |
US10255216B1 (en) * | 2013-11-19 | 2019-04-09 | Everspin Technologies, Inc. | Multiplexed memory in a communication processing system |
US9019754B1 (en) | 2013-12-17 | 2015-04-28 | Micron Technology, Inc. | State determination in resistance variable memory |
US9299412B2 (en) * | 2014-02-26 | 2016-03-29 | Intel Corporation | Write operations in spin transfer torque memory |
US9236560B1 (en) | 2014-12-08 | 2016-01-12 | Western Digital (Fremont), Llc | Spin transfer torque tunneling magnetoresistive device having a laminated free layer with perpendicular magnetic anisotropy |
US9281043B1 (en) | 2014-12-24 | 2016-03-08 | Intel Corporation | Resistive memory write circuitry with bit line drive strength based on storage cell line resistance |
US9805816B2 (en) * | 2015-04-03 | 2017-10-31 | Headway Technologies, Inc. | Implementation of a one time programmable memory using a MRAM stack design |
JP2017199443A (ja) * | 2016-04-27 | 2017-11-02 | ソニー株式会社 | 半導体記憶装置、駆動方法、および電子機器 |
WO2018026815A1 (en) | 2016-08-01 | 2018-02-08 | The Regents Of The University Of California | Memory write and read assistance using negative differential resistance devices |
TWI600009B (zh) * | 2016-11-04 | 2017-09-21 | 財團法人工業技術研究院 | 可變電阻記憶體電路以及可變電阻記憶體電路之寫入方法 |
US10360948B2 (en) | 2017-06-26 | 2019-07-23 | Samsung Electronics Co., Ltd. | Memory device and operating method of memory device |
KR102435906B1 (ko) | 2017-06-26 | 2022-08-24 | 삼성전자주식회사 | 메모리 장치 및 메모리 장치의 동작 방법 |
WO2019005162A1 (en) * | 2017-06-30 | 2019-01-03 | Intel Corporation | VOLATILE FILAMENT OXIDE FOR MAGNETIC TUNNEL JUNCTION MEMORY DEVICE (MTJ) AND METHODS OF FORMING THE SAME |
KR102360213B1 (ko) | 2017-09-06 | 2022-02-08 | 삼성전자주식회사 | 칩 사이즈를 감소한 저항성 메모리 장치 및 그 동작방법 |
US10326073B1 (en) | 2017-12-29 | 2019-06-18 | Spin Memory, Inc. | Spin hall effect (SHE) assisted three-dimensional spin transfer torque magnetic random access memory (STT-MRAM) |
US10693056B2 (en) | 2017-12-28 | 2020-06-23 | Spin Memory, Inc. | Three-dimensional (3D) magnetic memory device comprising a magnetic tunnel junction (MTJ) having a metallic buffer layer |
US10541268B2 (en) | 2017-12-28 | 2020-01-21 | Spin Memory, Inc. | Three-dimensional magnetic memory devices |
US10797233B2 (en) | 2017-12-29 | 2020-10-06 | Spin Memory, Inc. | Methods of fabricating three-dimensional magnetic memory devices |
US10424357B2 (en) | 2017-12-29 | 2019-09-24 | Spin Memory, Inc. | Magnetic tunnel junction (MTJ) memory device having a composite free magnetic layer |
US10347308B1 (en) | 2017-12-29 | 2019-07-09 | Spin Memory, Inc. | Systems and methods utilizing parallel configurations of magnetic memory devices |
US10803916B2 (en) | 2017-12-29 | 2020-10-13 | Spin Memory, Inc. | Methods and systems for writing to magnetic memory devices utilizing alternating current |
US10403343B2 (en) | 2017-12-29 | 2019-09-03 | Spin Memory, Inc. | Systems and methods utilizing serial configurations of magnetic memory devices |
US10319424B1 (en) | 2018-01-08 | 2019-06-11 | Spin Memory, Inc. | Adjustable current selectors |
US10192788B1 (en) | 2018-01-08 | 2019-01-29 | Spin Transfer Technologies | Methods of fabricating dual threshold voltage devices with stacked gates |
US10192789B1 (en) | 2018-01-08 | 2019-01-29 | Spin Transfer Technologies | Methods of fabricating dual threshold voltage devices |
US10770510B2 (en) * | 2018-01-08 | 2020-09-08 | Spin Memory, Inc. | Dual threshold voltage devices having a first transistor and a second transistor |
US10497415B2 (en) | 2018-01-08 | 2019-12-03 | Spin Memory, Inc. | Dual gate memory devices |
US10192787B1 (en) | 2018-01-08 | 2019-01-29 | Spin Transfer Technologies | Methods of fabricating contacts for cylindrical devices |
US10878870B2 (en) | 2018-09-28 | 2020-12-29 | Spin Memory, Inc. | Defect propagation structure and mechanism for magnetic memory |
US10692556B2 (en) | 2018-09-28 | 2020-06-23 | Spin Memory, Inc. | Defect injection structure and mechanism for magnetic memory |
CN112863575B (zh) * | 2019-11-12 | 2023-12-29 | 上海磁宇信息科技有限公司 | 具有磁性隧道结的非易失寄存器 |
CN112199041B (zh) * | 2020-09-24 | 2022-05-17 | 浙江驰拓科技有限公司 | 存储元件、存储电路、数据存取方法及数据存取装置 |
US11398262B1 (en) | 2021-04-16 | 2022-07-26 | Sandisk Technologies Llc | Forced current access with voltage clamping in cross-point array |
Family Cites Families (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3085782B2 (ja) * | 1992-05-29 | 2000-09-11 | 株式会社東芝 | 半導体記憶装置 |
JP2000285672A (ja) * | 1999-03-26 | 2000-10-13 | Fujitsu Ltd | メモリデバイス |
US6724652B2 (en) * | 2002-05-02 | 2004-04-20 | Micron Technology, Inc. | Low remanence flux concentrator for MRAM devices |
JP2004079033A (ja) * | 2002-08-12 | 2004-03-11 | Renesas Technology Corp | 不揮発性半導体記憶装置 |
KR100448246B1 (ko) * | 2002-09-09 | 2004-09-13 | 주식회사 하이닉스반도체 | 고전압 제어 장치 |
JP2004118923A (ja) * | 2002-09-25 | 2004-04-15 | Toshiba Corp | 磁気ランダムアクセスメモリ |
WO2004061854A1 (ja) * | 2003-01-06 | 2004-07-22 | Nec Corporation | 半導体記憶装置 |
KR100542709B1 (ko) | 2003-05-29 | 2006-01-11 | 주식회사 하이닉스반도체 | 반도체 메모리 소자의 부스팅 회로 |
JP2005101466A (ja) * | 2003-09-26 | 2005-04-14 | Renesas Technology Corp | 半導体記憶装置 |
JP4962828B2 (ja) * | 2004-08-25 | 2012-06-27 | マイクロン テクノロジー, インク. | ワード線ドライバ回路およびこれを利用する方法 |
JP4247170B2 (ja) * | 2004-09-02 | 2009-04-02 | 株式会社東芝 | 半導体記憶装置 |
US7085190B2 (en) * | 2004-09-16 | 2006-08-01 | Stmicroelectronics, Inc. | Variable boost voltage row driver circuit and method, and memory device and system including same |
JP4957913B2 (ja) * | 2005-11-17 | 2012-06-20 | 日本電気株式会社 | 半導体集積回路 |
JP2007184063A (ja) * | 2006-01-10 | 2007-07-19 | Renesas Technology Corp | 不揮発性半導体記憶装置 |
US7515457B2 (en) | 2006-02-24 | 2009-04-07 | Grandis, Inc. | Current driven memory cells having enhanced current and enhanced current symmetry |
KR100816748B1 (ko) * | 2006-03-16 | 2008-03-27 | 삼성전자주식회사 | 프로그램 서스펜드/리줌 모드를 지원하는 상 변화 메모리장치 및 그것의 프로그램 방법 |
US7345912B2 (en) * | 2006-06-01 | 2008-03-18 | Grandis, Inc. | Method and system for providing a magnetic memory structure utilizing spin transfer |
US7742329B2 (en) | 2007-03-06 | 2010-06-22 | Qualcomm Incorporated | Word line transistor strength control for read and write in spin transfer torque magnetoresistive random access memory |
US8133745B2 (en) * | 2007-10-17 | 2012-03-13 | Magic Technologies, Inc. | Method of magnetic tunneling layer processes for spin-transfer torque MRAM |
-
2008
- 2008-11-05 US US12/265,044 patent/US8107280B2/en active Active
-
2009
- 2009-11-04 EP EP09748663.3A patent/EP2353164B1/en active Active
- 2009-11-04 ES ES09748663.3T patent/ES2532396T3/es active Active
- 2009-11-04 BR BRPI0921432-1A patent/BRPI0921432B1/pt active IP Right Grant
- 2009-11-04 JP JP2011533439A patent/JP5185446B2/ja active Active
- 2009-11-04 WO PCT/US2009/063245 patent/WO2010053970A1/en active Application Filing
- 2009-11-04 CN CN200980144341.3A patent/CN102203870B/zh active Active
- 2009-11-04 KR KR1020117012971A patent/KR101257339B1/ko active IP Right Grant
- 2009-11-05 TW TW098137623A patent/TWI436360B/zh active
Also Published As
Publication number | Publication date |
---|---|
JP2012506602A (ja) | 2012-03-15 |
KR101257339B1 (ko) | 2013-04-23 |
WO2010053970A1 (en) | 2010-05-14 |
EP2353164B1 (en) | 2014-12-17 |
US8107280B2 (en) | 2012-01-31 |
CN102203870B (zh) | 2015-04-22 |
BRPI0921432A2 (pt) | 2018-05-29 |
TWI436360B (zh) | 2014-05-01 |
ES2532396T3 (es) | 2015-03-26 |
EP2353164A1 (en) | 2011-08-10 |
BRPI0921432B1 (pt) | 2020-10-06 |
KR20110093865A (ko) | 2011-08-18 |
US20100110775A1 (en) | 2010-05-06 |
TW201030745A (en) | 2010-08-16 |
CN102203870A (zh) | 2011-09-28 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5185446B2 (ja) | Stt−mramのワードライン電圧制御 | |
US7742329B2 (en) | Word line transistor strength control for read and write in spin transfer torque magnetoresistive random access memory | |
JP5643230B2 (ja) | スピン注入トルク磁気抵抗ランダムアクセスメモリでのビットラインの電圧制御 | |
JP5096502B2 (ja) | スピン転移トルク磁気抵抗ランダムアクセスメモリのための読出し障害減少回路 | |
US8582353B2 (en) | Nonvolatile memory device | |
US8159864B2 (en) | Data integrity preservation in spin transfer torque magnetoresistive random access memory | |
US20090103354A1 (en) | Ground Level Precharge Bit Line Scheme for Read Operation in Spin Transfer Torque Magnetoresistive Random Access Memory |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20121217 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20121221 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20130117 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 5185446 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20160125 Year of fee payment: 3 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |