JP5181626B2 - 多層プリント基板およびインバータ装置 - Google Patents

多層プリント基板およびインバータ装置 Download PDF

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Publication number
JP5181626B2
JP5181626B2 JP2007286911A JP2007286911A JP5181626B2 JP 5181626 B2 JP5181626 B2 JP 5181626B2 JP 2007286911 A JP2007286911 A JP 2007286911A JP 2007286911 A JP2007286911 A JP 2007286911A JP 5181626 B2 JP5181626 B2 JP 5181626B2
Authority
JP
Japan
Prior art keywords
chip
circuit board
package
printed circuit
multilayer printed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2007286911A
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English (en)
Japanese (ja)
Other versions
JP2009117501A5 (https=
JP2009117501A (ja
Inventor
友和 本田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Yaskawa Electric Corp
Original Assignee
Yaskawa Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Yaskawa Electric Corp filed Critical Yaskawa Electric Corp
Priority to JP2007286911A priority Critical patent/JP5181626B2/ja
Publication of JP2009117501A publication Critical patent/JP2009117501A/ja
Publication of JP2009117501A5 publication Critical patent/JP2009117501A5/ja
Application granted granted Critical
Publication of JP5181626B2 publication Critical patent/JP5181626B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H10W72/247—Dispositions of multiple bumps
    • H10W72/248—Top-view layouts, e.g. mirror arrays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5524—Materials of bond wires comprising metals or metalloids, e.g. silver comprising aluminium [Al]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
JP2007286911A 2007-11-05 2007-11-05 多層プリント基板およびインバータ装置 Expired - Fee Related JP5181626B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2007286911A JP5181626B2 (ja) 2007-11-05 2007-11-05 多層プリント基板およびインバータ装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2007286911A JP5181626B2 (ja) 2007-11-05 2007-11-05 多層プリント基板およびインバータ装置

Publications (3)

Publication Number Publication Date
JP2009117501A JP2009117501A (ja) 2009-05-28
JP2009117501A5 JP2009117501A5 (https=) 2011-08-18
JP5181626B2 true JP5181626B2 (ja) 2013-04-10

Family

ID=40784320

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007286911A Expired - Fee Related JP5181626B2 (ja) 2007-11-05 2007-11-05 多層プリント基板およびインバータ装置

Country Status (1)

Country Link
JP (1) JP5181626B2 (https=)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4973761B2 (ja) 2009-05-25 2012-07-11 株式会社デンソー 半導体装置
JP6007485B2 (ja) * 2011-12-05 2016-10-12 大日本印刷株式会社 部品内蔵配線基板、及びその製造方法
CN205093051U (zh) 2013-05-14 2016-03-16 株式会社村田制作所 部件内置基板以及通信模块
US12193161B2 (en) * 2020-06-01 2025-01-07 Steering Solutions Ip Holding Corporation Redundant printed circuit board with built in isolation

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005317903A (ja) * 2004-03-31 2005-11-10 Alps Electric Co Ltd 回路部品モジュール、回路部品モジュールスタック、記録媒体およびこれらの製造方法
JP4285364B2 (ja) * 2004-08-20 2009-06-24 パナソニック株式会社 立体回路モジュールとこれを用いた携帯端末機器および立体回路モジュールの製造方法
JP2006310421A (ja) * 2005-04-27 2006-11-09 Cmk Corp 部品内蔵型プリント配線板とその製造方法
JP2007227586A (ja) * 2006-02-23 2007-09-06 Cmk Corp 半導体素子内蔵基板及びその製造方法

Also Published As

Publication number Publication date
JP2009117501A (ja) 2009-05-28

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