JP5167022B2 - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法 Download PDF

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Publication number
JP5167022B2
JP5167022B2 JP2008204141A JP2008204141A JP5167022B2 JP 5167022 B2 JP5167022 B2 JP 5167022B2 JP 2008204141 A JP2008204141 A JP 2008204141A JP 2008204141 A JP2008204141 A JP 2008204141A JP 5167022 B2 JP5167022 B2 JP 5167022B2
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JP
Japan
Prior art keywords
sealing body
metal substrate
substrate
metal
molding die
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2008204141A
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English (en)
Japanese (ja)
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JP2010040911A5 (enExample
JP2010040911A (ja
Inventor
孝治 古川
嗣雄 原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Electronics Corp
Original Assignee
Renesas Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Electronics Corp filed Critical Renesas Electronics Corp
Priority to JP2008204141A priority Critical patent/JP5167022B2/ja
Publication of JP2010040911A publication Critical patent/JP2010040911A/ja
Publication of JP2010040911A5 publication Critical patent/JP2010040911A5/ja
Application granted granted Critical
Publication of JP5167022B2 publication Critical patent/JP5167022B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
JP2008204141A 2008-08-07 2008-08-07 半導体装置の製造方法 Expired - Fee Related JP5167022B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2008204141A JP5167022B2 (ja) 2008-08-07 2008-08-07 半導体装置の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2008204141A JP5167022B2 (ja) 2008-08-07 2008-08-07 半導体装置の製造方法

Publications (3)

Publication Number Publication Date
JP2010040911A JP2010040911A (ja) 2010-02-18
JP2010040911A5 JP2010040911A5 (enExample) 2011-09-15
JP5167022B2 true JP5167022B2 (ja) 2013-03-21

Family

ID=42013110

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008204141A Expired - Fee Related JP5167022B2 (ja) 2008-08-07 2008-08-07 半導体装置の製造方法

Country Status (1)

Country Link
JP (1) JP5167022B2 (enExample)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6466252B2 (ja) 2014-06-19 2019-02-06 株式会社ジェイデバイス 半導体パッケージ及びその製造方法
JP6457206B2 (ja) 2014-06-19 2019-01-23 株式会社ジェイデバイス 半導体パッケージ及びその製造方法
CN105280567B (zh) 2014-06-19 2018-12-28 株式会社吉帝伟士 半导体封装件及其制造方法
JP6304435B1 (ja) * 2017-07-25 2018-04-04 第一精工株式会社 基材の変形止め機構及び基材の変形止め方法
CN117939794B (zh) * 2024-03-20 2024-05-28 大连保税区金宝至电子有限公司 一种分布式外引脚覆铜陶瓷基板的加工方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62124747A (ja) * 1985-11-25 1987-06-06 Sharp Corp 自動モ−ルド装置に於けるカルブレイク方法
JP2000299329A (ja) * 1999-04-12 2000-10-24 Mitsubishi Electric Corp 樹脂パッケージ型半導体装置の製造装置及び製造方法
JP4106844B2 (ja) * 2000-02-22 2008-06-25 沖電気工業株式会社 樹脂封止半導体装置のリード部のゲートブレーク方法
JP2002016181A (ja) * 2000-04-25 2002-01-18 Torex Semiconductor Ltd 半導体装置、その製造方法、及び電着フレーム
JP2004214265A (ja) * 2002-12-27 2004-07-29 Kyushu Hitachi Maxell Ltd 半導体装置および半導体装置の製造方法
JP2006269486A (ja) * 2005-03-22 2006-10-05 Renesas Technology Corp 半導体装置の製造方法
JP2006351835A (ja) * 2005-06-16 2006-12-28 Aoi Electronics Co Ltd 半導体装置および半導体装置の製造方法

Also Published As

Publication number Publication date
JP2010040911A (ja) 2010-02-18

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