JP5149301B2 - 引張歪みおよび圧縮歪みを生成するための埋め込みSi/Ge材料を含むNMOSトランジスタおよびPMOSトランジスタを有する半導体デバイス - Google Patents
引張歪みおよび圧縮歪みを生成するための埋め込みSi/Ge材料を含むNMOSトランジスタおよびPMOSトランジスタを有する半導体デバイス Download PDFInfo
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- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
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- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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Description
Claims (8)
- 半導体層(102;202;302)の第1能動領域および第2能動領域(105A,105B)の材料を除去するために、前記第1能動領域および前記第2能動領域(105A,105B)を画定している分離構造(103)に対して選択的なエッチング環境(106)に前記第1能動領域および前記第2能動領域(105A,105B)を露出させることによって、前記第1の能動領域(105A)に第1の開口部(106A)を、前記第2の能動領域(105B)に第2の開口部(106B)を形成するステップと、
前記第1の開口および前記第2の開口(106A,106B)内に半導体合金(107;207;307)を形成するステップと、
前記第2能動領域(105B)の前記半導体合金(107;207;307)の中央部分を選択的に除去して、前記半導体合金(107;207;307)の第1の部分と第2の部分の間に形成される中央領域(107;207;307)を画定するステップと、
前記第1能動領域(105A)の少なくとも一部の上に半導体材料層(113A;213A;313A)を形成するステップと、
前記中央領域(107;207;307)に前記半導体材料(113B;213B;313B)を埋め込むステップと、を含む方法。 - 前記第1能動領域(105A)の上に第1ゲート電極(121,221,321)を、前記第2能動領域(105B)の上に第2ゲート電極(121,221,321)を形成するステップを更に含み、前記第2ゲート電極は前記中央領域(107B;207B;307B)の上に位置している請求項1に記載の方法。
- 前記第1能動領域上に前記半導体材料層(113A,213A,313A)を形成するステップは、前記第1能動領域に前記半導体合金(107,207,307)が導入されている凹部を形成するステップを含む請求項1に記載の方法。
- 前記半導体材料層(113A,213A,313A)を形成するステップは第1のマスク層(108)を基に実施され、前記中央領域(107B;207B;307B)に埋め込むステップは第2のマスク層(210)を基に実施される請求項1に記載の方法。
- 前記第1能動領域の上に第1の開口(308A)を、前記中央領域(307)の上に第2の開口(308B)を有するマスク層(308)を提供し、前記第1の開口および前記第2の開口(308A,308B)にゲート電極材料を埋め込むことによって第1ゲート電極および第2ゲート電極(121,221,321)を形成するステップを含む請求項1に記載の方法。
- 前記第2の開口(308B)を通る前記中央領域(307B)を画定するステップを更に含む請求項5に記載の方法。
- 前記第2の開口(308B)を覆っている第2のマスク材料(311)を基に前記マスク層(308)に前記第1の開口(308A)を形成するステップを更に含む請求項6に記載の方法。
- 前記第2の開口(308B)を通って前記中央領域(307B)に前記半導体材料(313B)を埋め込むステップと、
前記第1能動領域(305A)の上に前記半導体材料層(313A)を形成するステップと、
前記第2能動領域(305B)の上に別の半導体材料層(313B)を形成するステップと、を更に含む請求項7に記載の方法。
Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE102006051492A DE102006051492B4 (de) | 2006-10-31 | 2006-10-31 | Halbleiterbauelement mit NMOS- und PMOS-Transistoren mit eingebettetem Si/Ge-Material zum Erzeugen einer Zugverformung und einer Druckverformung und Verfahren zur Herstellung eines solchen Halbleiterbauelements |
DE102006051492.0 | 2006-10-31 | ||
US11/748,902 US7741167B2 (en) | 2006-10-31 | 2007-05-15 | Semiconductor device comprising NMOS and PMOS transistors with embedded Si/Ge material for creating tensile and compressive strain |
US11/748,902 | 2007-05-15 | ||
PCT/US2007/022680 WO2008054678A1 (en) | 2006-10-31 | 2007-10-26 | A semiconductor device comprising nmos and pmos transistors with embedded si/ge material for creating tensile and compressive strain |
Publications (2)
Publication Number | Publication Date |
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JP2010508671A JP2010508671A (ja) | 2010-03-18 |
JP5149301B2 true JP5149301B2 (ja) | 2013-02-20 |
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Application Number | Title | Priority Date | Filing Date |
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JP2009535278A Active JP5149301B2 (ja) | 2006-10-31 | 2007-10-26 | 引張歪みおよび圧縮歪みを生成するための埋め込みSi/Ge材料を含むNMOSトランジスタおよびPMOSトランジスタを有する半導体デバイス |
Country Status (6)
Country | Link |
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US (3) | US7741167B2 (ja) |
JP (1) | JP5149301B2 (ja) |
CN (1) | CN101632167B (ja) |
DE (1) | DE102006051492B4 (ja) |
GB (1) | GB2455960B (ja) |
TW (1) | TWI431760B (ja) |
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US8394687B2 (en) * | 2007-03-30 | 2013-03-12 | Intel Corporation | Ultra-abrupt semiconductor junction profile |
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EP2113940A1 (en) * | 2008-04-30 | 2009-11-04 | Imec | A method for producing NMOS and PMOS devices in CMOS processing |
US8114727B2 (en) * | 2008-08-29 | 2012-02-14 | Texas Instruments Incorporated | Disposable spacer integration with stress memorization technique and silicon-germanium |
DE102009006886B4 (de) * | 2009-01-30 | 2012-12-06 | Advanced Micro Devices, Inc. | Verringerung von Dickenschwankungen einer schwellwerteinstellenden Halbleiterlegierung durch Verringern der Strukturierungsungleichmäßigkeiten vor dem Abscheiden der Halbleiterlegierung |
WO2010086152A1 (en) * | 2009-01-30 | 2010-08-05 | Advanced Micro Devices, Inc. | Reduction of thickness variations of a threshold adjusting semiconductor alloy by reducing patterning non-uniformities prior to depositing the semiconductor alloy |
DE102009021489B4 (de) | 2009-05-15 | 2012-01-12 | Globalfoundries Dresden Module One Llc & Co. Kg | Erhöhen der Abscheidegleichmäßigkeit für eine zur Schwellwerteinstellung in einem aktiven Gebiet vorgesehene Halbleiterlegierung |
US20110084355A1 (en) * | 2009-10-09 | 2011-04-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Isolation Structure For Semiconductor Device |
DE102009046241B4 (de) * | 2009-10-30 | 2012-12-06 | Globalfoundries Dresden Module One Limited Liability Company & Co. Kg | Verformungsverstärkung in Transistoren, die eine eingebettete verformungsinduzierende Halbleiterlegierung besitzen, durch Kantenverrundung an der Oberseite der Gateelektrode |
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