JP5147471B2 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
JP5147471B2
JP5147471B2 JP2008064435A JP2008064435A JP5147471B2 JP 5147471 B2 JP5147471 B2 JP 5147471B2 JP 2008064435 A JP2008064435 A JP 2008064435A JP 2008064435 A JP2008064435 A JP 2008064435A JP 5147471 B2 JP5147471 B2 JP 5147471B2
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Japan
Prior art keywords
film
insulating film
gate electrode
semiconductor device
gate
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JP2008064435A
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English (en)
Japanese (ja)
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JP2009224386A (ja
JP2009224386A5 (enExample
Inventor
好弘 佐藤
久 小川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Corp
Panasonic Holdings Corp
Original Assignee
Panasonic Corp
Matsushita Electric Industrial Co Ltd
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Application filed by Panasonic Corp, Matsushita Electric Industrial Co Ltd filed Critical Panasonic Corp
Priority to JP2008064435A priority Critical patent/JP5147471B2/ja
Priority to PCT/JP2009/000574 priority patent/WO2009113241A1/ja
Publication of JP2009224386A publication Critical patent/JP2009224386A/ja
Priority to US12/629,508 priority patent/US8198686B2/en
Publication of JP2009224386A5 publication Critical patent/JP2009224386A5/ja
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28088—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a composite, e.g. TiN
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/027—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs
    • H10D30/0275—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs forming single crystalline semiconductor source or drain regions resulting in recessed gates, e.g. forming raised source or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
    • H10D30/792—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions comprising applied insulating layers, e.g. stress liners
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
    • H10D30/797—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions being in source or drain regions, e.g. SiGe source or drain
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/01—Manufacture or treatment
    • H10D62/021—Forming source or drain recesses by etching e.g. recessing by etching and then refilling
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/015—Manufacture or treatment removing at least parts of gate spacers, e.g. disposable spacers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/017—Manufacture or treatment using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/667—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0167—Manufacturing their channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/017—Manufacturing their source or drain regions, e.g. silicided source or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0172—Manufacturing their gate conductors
    • H10D84/0177—Manufacturing their gate conductors the gate conductors having different materials or different implants
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0212—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/82—Heterojunctions
    • H10D62/822—Heterojunctions comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/018—Spacers formed inside holes at the prospective gate locations, e.g. holes left by removing dummy gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/021—Manufacture or treatment using multiple gate spacer layers, e.g. bilayered sidewall spacers

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Composite Materials (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
JP2008064435A 2008-03-13 2008-03-13 半導体装置 Active JP5147471B2 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2008064435A JP5147471B2 (ja) 2008-03-13 2008-03-13 半導体装置
PCT/JP2009/000574 WO2009113241A1 (ja) 2008-03-13 2009-02-13 半導体装置及びその製造方法
US12/629,508 US8198686B2 (en) 2008-03-13 2009-12-02 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2008064435A JP5147471B2 (ja) 2008-03-13 2008-03-13 半導体装置

Publications (3)

Publication Number Publication Date
JP2009224386A JP2009224386A (ja) 2009-10-01
JP2009224386A5 JP2009224386A5 (enExample) 2010-04-08
JP5147471B2 true JP5147471B2 (ja) 2013-02-20

Family

ID=41064914

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008064435A Active JP5147471B2 (ja) 2008-03-13 2008-03-13 半導体装置

Country Status (3)

Country Link
US (1) US8198686B2 (enExample)
JP (1) JP5147471B2 (enExample)
WO (1) WO2009113241A1 (enExample)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5349903B2 (ja) * 2008-02-28 2013-11-20 ルネサスエレクトロニクス株式会社 半導体装置の製造方法および半導体装置
JP5287539B2 (ja) * 2009-06-23 2013-09-11 富士通セミコンダクター株式会社 半導体装置の製造方法
DE102009055435B4 (de) * 2009-12-31 2017-11-09 Globalfoundries Dresden Module One Limited Liability Company & Co. Kg Verstärkter Einschluss von Metallgateelektrodenstrukturen mit großem ε durch Verringern der Materialerosion einer dielektrischen Deckschicht beim Erzeugen einer verformungsinduzierenden Halbleiterlegierung
DE102010001406B4 (de) 2010-01-29 2014-12-11 GLOBALFOUNDRIES Dresden Module One Ltd. Liability Company & Co. KG Austausch-Gate-Verfahren auf der Grundlage eines früh aufgebrachten Austrittsarbeitsmetalls
JP5503735B2 (ja) * 2010-03-30 2014-05-28 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
KR101815527B1 (ko) * 2010-10-07 2018-01-05 삼성전자주식회사 반도체 소자 및 그 제조 방법
JP2012099517A (ja) 2010-10-29 2012-05-24 Sony Corp 半導体装置及び半導体装置の製造方法
DE102011003385B4 (de) 2011-01-31 2015-12-03 Globalfoundries Dresden Module One Limited Liability Company & Co. Kg Verfahren zur Herstellung einer Halbleiterstruktur mit verformungsinduzierendem Halbleitermaterial
US8421132B2 (en) * 2011-05-09 2013-04-16 International Business Machines Corporation Post-planarization UV curing of stress inducing layers in replacement gate transistor fabrication
US9018090B2 (en) * 2011-10-10 2015-04-28 International Business Machines Corporation Borderless self-aligned metal contact patterning using printable dielectric materials
US9196708B2 (en) 2013-12-30 2015-11-24 Taiwan Semiconductor Manufacturing Co., Ltd Method for forming a semiconductor device structure
US9620384B2 (en) * 2014-07-03 2017-04-11 Globalfoundries Inc. Control of O-ingress into gate stack dielectric layer using oxygen permeable layer
US9589806B1 (en) * 2015-10-19 2017-03-07 Globalfoundries Inc. Integrated circuit with replacement gate stacks and method of forming same
FR3050315B1 (fr) * 2016-04-19 2019-06-21 Commissariat A L'energie Atomique Et Aux Energies Alternatives Transistor a overlap des regions d'acces maitrise
FR3069370B1 (fr) * 2017-07-21 2021-10-22 St Microelectronics Rousset Circuit integre contenant une structure de leurre

Family Cites Families (16)

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Publication number Priority date Publication date Assignee Title
US6184083B1 (en) * 1997-06-30 2001-02-06 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing the same
JPH1174368A (ja) * 1997-06-30 1999-03-16 Toshiba Corp 半導体装置および半導体装置の製造方法
US6261887B1 (en) * 1997-08-28 2001-07-17 Texas Instruments Incorporated Transistors with independently formed gate structures and method
JP2002118175A (ja) * 2000-10-05 2002-04-19 Toshiba Corp 半導体装置及びその製造方法
US6420279B1 (en) * 2001-06-28 2002-07-16 Sharp Laboratories Of America, Inc. Methods of using atomic layer deposition to deposit a high dielectric constant material on a substrate
JP4011024B2 (ja) * 2004-01-30 2007-11-21 株式会社ルネサステクノロジ 半導体装置およびその製造方法
JP4375619B2 (ja) * 2004-05-26 2009-12-02 富士通マイクロエレクトロニクス株式会社 半導体装置の製造方法
DE102004052617B4 (de) * 2004-10-29 2010-08-05 Advanced Micro Devices, Inc., Sunnyvale Verfahren zur Herstellung eines Halbleiterbauelements und Halbleiterbauelement mit Halbleitergebieten, die unterschiedlich verformte Kanalgebiete aufweisen
KR20070069160A (ko) * 2004-10-29 2007-07-02 어드밴스드 마이크로 디바이시즈, 인코포레이티드 서로 다른 스트레인드 채널 영역들을 갖는 반도체 영역들을포함하는 반도체 디바이스 및 이를 제조하는 방법
JP4369379B2 (ja) * 2005-02-18 2009-11-18 富士通マイクロエレクトロニクス株式会社 半導体装置
JP4723975B2 (ja) * 2005-10-25 2011-07-13 株式会社東芝 半導体装置およびその製造方法
JP2007201063A (ja) * 2006-01-25 2007-08-09 Matsushita Electric Ind Co Ltd 半導体装置及びその製造方法
JP5055779B2 (ja) * 2006-02-09 2012-10-24 ソニー株式会社 半導体装置の製造方法
JP2007258267A (ja) * 2006-03-20 2007-10-04 Toshiba Corp 半導体装置及びその製造方法
JP2007288096A (ja) * 2006-04-20 2007-11-01 Matsushita Electric Ind Co Ltd 半導体装置及びその製造方法
US7812414B2 (en) * 2007-01-23 2010-10-12 Taiwan Semiconductor Manufacturing Company, Ltd. Hybrid process for forming metal gates

Also Published As

Publication number Publication date
JP2009224386A (ja) 2009-10-01
WO2009113241A1 (ja) 2009-09-17
US20100072523A1 (en) 2010-03-25
US8198686B2 (en) 2012-06-12

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