JP5113316B2 - 仮想接地アレイ・不揮発性半導体メモリ装置を形成する方法 - Google Patents
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/42—Simultaneous manufacture of periphery and memory cells
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
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Description
小型化と高速アクセスに対する要求により、EEPROM(電気的消去可能プログラマブル・リードオンリーメモリ)フラッシュメモリデバイスの開発が進められてきた。そのような開発成果の一つに、従来型およびSONOS(シリコン−酸化物−窒化物−酸化物−シリコン)フラッシュメモリデバイスの両方に適用可能な、仮想接地アレイ(virtual ground array)構造がある。非仮想接地アレイ構造は、読み出しおよび書き込み動作専用のソースおよびドレイン領域を持つのに対し、仮想接地アレイ構造は、印加電圧に応じてソースとしてもドレインとしても用いることができるビット線を採用することによって、ゲートとゲートの間隔を小さくする。
一般的に、メモリ装置はこれまでよりもより速く、そして小型化されている。しかしながら、さらに速く、および/または、より小型のメモリ装置に対する要求は尽きることがない。
電荷トラップ絶縁体スタックは、SONOSメモリセルスタックの電荷トラップ部分であってもよい。図5に、SONOSメモリセルスタック500の一例を示す。SONOSメモリセルスタック500は、基板502上に形成された、電荷トラップ絶縁体504およびポリ層506とを含む。電荷トラップ絶縁体は、電子の捕獲(トラップ)が可能な、またはそれを促進するどのような絶縁体の層または複数の層であってもよい。言い換えれば、電子の捕獲を促進するために、電荷トラップ絶縁体は、それをサンドイッチする層よりも低い障壁高さ(barrier height)を持つ層を持つ(比較的高い障壁高さを持つ2つの層が比較的低い障壁高さを持つ層をサンドイッチする)。ONO三層絶縁体の場合、酸化物層がおおよそ3.1eVの障壁高さを持つのに対し、窒化物層はおおよそ2.1eVの障壁高さを持つ。この結合によって、中間層にウェルが形成される。
本発明の一実施例において、酸化物層は独立しておおよそ50オングストロームからおおよそ150オングストロームの厚さを持ち、窒化物層はおおよそ20オングストロームからおおよそ80オングストロームの厚さを持つ。本発明の他の実施例において、酸化物層は独立しておおよそ60オングストロームからおおよそ140オングストロームの厚さを持ち、窒化物層はおおよそ25オングストロームからおおよそ75オングストロームの厚さを持つ。本発明のさらに他の実施例において、酸化物層は独立しておおよそ70オングストロームからおおよそ130オングストロームの厚さを持ち、窒化物層はおおよそ30オングストロームからおおよそ70オングストロームの厚さを持つ。
場合によっては、処理408と処理410とを同時に実行することもできる。この場合、その場の(in situ)ドーピング形成技術が用いられる。
スパッタリングのデポジションでは、デポジションされる金属をエネルギーが与えられたイオンで爆撃して(bombard)、いくらかの原子を解放する。これらの原子が基板上で凝集して膜を形成する。CVDでは、気相または基板の表面上で起こる一以上の反応によって、金属が生成される。これらの反応は、一般的に熱によって誘導されるが、これは化合物を含む金属の分解、または異なった種の間の反応を引き起こす。金属有機化合物がCVDプロセスでは有用である。
Claims (8)
- 仮想接地アレイ・不揮発性半導体メモリ装置を形成する方法であって、
酸化物アイランドが形成されていないコア領域および周辺領域を持つ半導体基板(702)を準備するステップと、
前記酸化物アイランドが形成されていないコア領域上に、少なくとも一つの絶縁体層を含む電荷トラップ層(706)を形成するステップと、
前記コア領域の前記基板(702)をドーピングすることによって酸化物アイランドを形成することなく埋込みビット線を形成するステップと、
少なくとも前記電荷トラップ層(706)の上にポリ層(708)を形成するステップと、
前記コア領域内において前記ポリ層(708)をパターン化する前に、前記コア領域内の前記ポリ層(708)をドーピングしてワード線間の基板部分がドープされないようにするステップと、
前記コア領域内の前記ポリ層(708)をパターン化して、前記ワード線を形成するステップと、
前記コア領域をマスクするステップと、
前記コア領域がマスクされているときに、前記ワード線をサリサイド処理する前に、前記基板(702)をドープして、前記周辺領域内のゲートに近接するソースおよびドレイン領域を形成するステップと、
前記ワード線間の前記半導体基板を露出させずに前記ワード線を露出させた上で前記ワード線をサリサイド処理するステップと、を含み、
前記周辺領域内のゲートに近接するソースおよびドレイン領域が、前記コア領域内の前記ワード線と同時にサリサイド処理される方法。 - 仮想接地アレイ・不揮発性半導体メモリ装置はNOR装置構造を含む、請求項1記載の方法。
- 仮想接地アレイ・不揮発性半導体メモリ装置はSONOSメモリ装置を含む、請求項1記載の方法。
- 仮想接地アレイ・不揮発性半導体メモリ装置を形成する方法であって、
酸化物アイランドが形成されていないコア領域および周辺領域を持つ半導体基板(702)を準備するステップと、
前記酸化物アイランドが形成されていないコア領域上に、少なくとも一つの絶縁体層を含む電荷トラップ層(706)を形成するステップと、
前記コア領域の前記基板(702)をドーピングすることによって酸化物アイランドを形成することなく埋込みビット線を形成するステップと、
少なくとも前記電荷トラップ層(706)の上にポリ層(708)を形成するステップと、
前記コア領域内のポリ層(708)をパターン化して、基板上に間隔が設けられた複数のワード線を形成するステップと、
前記ワード線間の前記半導体基板を露出させずに前記ワード線を露出させた上で前記ワード線をサリサイド処理するステップと、を含み、
前記周辺領域内のゲートに近接するソースおよびドレイン領域が、前記コア領域内の前記ワード線と同時にサリサイド処理される方法。 - 仮想接地アレイ・不揮発性半導体メモリ装置はNOR装置構造を含む、請求項4記載の方法。
- 仮想接地アレイ・不揮発性半導体メモリ装置はSONOSメモリ装置を含む、請求項4記載の方法。
- 前記ワード線がサリサイド処理される間に、少なくとも前記絶縁体層が前記ワード線の間の前記半導体基板をサリサイド化されないように保護する、請求項4記載の方法。
- 前記ワード線がサリサイド処理される間に、少なくともスペーサー材料が前記ワード線の間の前記半導体基板をサリサイド化されないように保護する、請求項4記載の方法。
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US09/968,465 US6566194B1 (en) | 2001-10-01 | 2001-10-01 | Salicided gate for virtual ground arrays |
US09/968,465 | 2001-10-01 | ||
PCT/US2002/030784 WO2003030253A2 (en) | 2001-10-01 | 2002-09-27 | Salicided gate for virtual ground arrays |
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EP (1) | EP1435114B1 (ja) |
JP (1) | JP5113316B2 (ja) |
KR (1) | KR20040037228A (ja) |
CN (1) | CN1610972A (ja) |
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-
2001
- 2001-10-01 US US09/968,465 patent/US6566194B1/en not_active Expired - Lifetime
-
2002
- 2002-09-27 JP JP2003533343A patent/JP5113316B2/ja not_active Expired - Lifetime
- 2002-09-27 DE DE60238549T patent/DE60238549D1/de not_active Expired - Lifetime
- 2002-09-27 WO PCT/US2002/030784 patent/WO2003030253A2/en active Application Filing
- 2002-09-27 AU AU2002337732A patent/AU2002337732A1/en not_active Abandoned
- 2002-09-27 CN CNA028190750A patent/CN1610972A/zh active Pending
- 2002-09-27 EP EP02773624A patent/EP1435114B1/en not_active Expired - Fee Related
- 2002-09-27 KR KR10-2004-7004809A patent/KR20040037228A/ko not_active Application Discontinuation
- 2002-10-01 TW TW091122597A patent/TW561532B/zh not_active IP Right Cessation
Also Published As
Publication number | Publication date |
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CN1610972A (zh) | 2005-04-27 |
US6566194B1 (en) | 2003-05-20 |
WO2003030253A2 (en) | 2003-04-10 |
WO2003030253A3 (en) | 2003-08-28 |
US20030085417A1 (en) | 2003-05-08 |
KR20040037228A (ko) | 2004-05-04 |
DE60238549D1 (de) | 2011-01-20 |
EP1435114A2 (en) | 2004-07-07 |
EP1435114B1 (en) | 2010-12-08 |
TW561532B (en) | 2003-11-11 |
AU2002337732A1 (en) | 2003-04-14 |
JP2005505922A (ja) | 2005-02-24 |
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