DE60238549D1 - Salizidgate für matrizen mit virtueller erdung - Google Patents
Salizidgate für matrizen mit virtueller erdungInfo
- Publication number
- DE60238549D1 DE60238549D1 DE60238549T DE60238549T DE60238549D1 DE 60238549 D1 DE60238549 D1 DE 60238549D1 DE 60238549 T DE60238549 T DE 60238549T DE 60238549 T DE60238549 T DE 60238549T DE 60238549 D1 DE60238549 D1 DE 60238549D1
- Authority
- DE
- Germany
- Prior art keywords
- matrices
- salicide gate
- earthing
- virtual
- virtual earthing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/42—Simultaneous manufacture of periphery and memory cells
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B99/00—Subject matter not provided for in other groups of this subclass
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US09/968,465 US6566194B1 (en) | 2001-10-01 | 2001-10-01 | Salicided gate for virtual ground arrays |
| PCT/US2002/030784 WO2003030253A2 (en) | 2001-10-01 | 2002-09-27 | Salicided gate for virtual ground arrays |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| DE60238549D1 true DE60238549D1 (de) | 2011-01-20 |
Family
ID=25514307
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE60238549T Expired - Lifetime DE60238549D1 (de) | 2001-10-01 | 2002-09-27 | Salizidgate für matrizen mit virtueller erdung |
Country Status (9)
| Country | Link |
|---|---|
| US (1) | US6566194B1 (de) |
| EP (1) | EP1435114B1 (de) |
| JP (1) | JP5113316B2 (de) |
| KR (1) | KR20040037228A (de) |
| CN (1) | CN1610972A (de) |
| AU (1) | AU2002337732A1 (de) |
| DE (1) | DE60238549D1 (de) |
| TW (1) | TW561532B (de) |
| WO (1) | WO2003030253A2 (de) |
Families Citing this family (27)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6768165B1 (en) * | 1997-08-01 | 2004-07-27 | Saifun Semiconductors Ltd. | Two bit non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping |
| US8673716B2 (en) * | 2002-04-08 | 2014-03-18 | Spansion Llc | Memory manufacturing process with bitline isolation |
| US6808992B1 (en) * | 2002-05-15 | 2004-10-26 | Spansion Llc | Method and system for tailoring core and periphery cells in a nonvolatile memory |
| US6917544B2 (en) | 2002-07-10 | 2005-07-12 | Saifun Semiconductors Ltd. | Multiple use memory chip |
| US6797565B1 (en) * | 2002-09-16 | 2004-09-28 | Advanced Micro Devices, Inc. | Methods for fabricating and planarizing dual poly scalable SONOS flash memory |
| US7136304B2 (en) | 2002-10-29 | 2006-11-14 | Saifun Semiconductor Ltd | Method, system and circuit for programming a non-volatile memory array |
| US7178004B2 (en) | 2003-01-31 | 2007-02-13 | Yan Polansky | Memory array programming circuit and a method for using the circuit |
| US6962849B1 (en) | 2003-12-05 | 2005-11-08 | Advanced Micro Devices, Inc. | Hard mask spacer for sublithographic bitline |
| US6958272B2 (en) * | 2004-01-12 | 2005-10-25 | Advanced Micro Devices, Inc. | Pocket implant for complementary bit disturb improvement and charging improvement of SONOS memory cell |
| US6872609B1 (en) | 2004-01-12 | 2005-03-29 | Advanced Micro Devices, Inc. | Narrow bitline using Safier for mirrorbit |
| US6989320B2 (en) * | 2004-05-11 | 2006-01-24 | Advanced Micro Devices, Inc. | Bitline implant utilizing dual poly |
| US7176113B1 (en) | 2004-06-07 | 2007-02-13 | Spansion Llc | LDC implant for mirrorbit to improve Vt roll-off and form sharper junction |
| US20060036803A1 (en) * | 2004-08-16 | 2006-02-16 | Mori Edan | Non-volatile memory device controlled by a micro-controller |
| CN1322579C (zh) * | 2004-09-10 | 2007-06-20 | 联华电子股份有限公司 | 制作分离编程虚拟接地sonos型存储器的方法 |
| US7638850B2 (en) | 2004-10-14 | 2009-12-29 | Saifun Semiconductors Ltd. | Non-volatile memory structure and method of fabrication |
| US8053812B2 (en) | 2005-03-17 | 2011-11-08 | Spansion Israel Ltd | Contact in planar NROM technology |
| US7786512B2 (en) | 2005-07-18 | 2010-08-31 | Saifun Semiconductors Ltd. | Dense non-volatile memory array and method of fabrication |
| US7668017B2 (en) | 2005-08-17 | 2010-02-23 | Saifun Semiconductors Ltd. | Method of erasing non-volatile memory cells |
| US20070087503A1 (en) * | 2005-10-17 | 2007-04-19 | Saifun Semiconductors, Ltd. | Improving NROM device characteristics using adjusted gate work function |
| US7808818B2 (en) | 2006-01-12 | 2010-10-05 | Saifun Semiconductors Ltd. | Secondary injection for NROM |
| US7760554B2 (en) | 2006-02-21 | 2010-07-20 | Saifun Semiconductors Ltd. | NROM non-volatile memory and mode of operation |
| US8253452B2 (en) | 2006-02-21 | 2012-08-28 | Spansion Israel Ltd | Circuit and method for powering up an integrated circuit and an integrated circuit utilizing same |
| US7692961B2 (en) | 2006-02-21 | 2010-04-06 | Saifun Semiconductors Ltd. | Method, circuit and device for disturb-control of programming nonvolatile memory cells by hot-hole injection (HHI) and by channel hot-electron (CHE) injection |
| US7701779B2 (en) | 2006-04-27 | 2010-04-20 | Sajfun Semiconductors Ltd. | Method for programming a reference cell |
| US7517737B2 (en) * | 2007-02-07 | 2009-04-14 | Macronix International Co., Ltd. | Structures for and method of silicide formation on memory array and peripheral logic devices |
| US8946018B2 (en) | 2012-08-21 | 2015-02-03 | Micron Technology, Inc. | Methods of forming memory arrays and semiconductor constructions |
| KR102051529B1 (ko) * | 2013-03-25 | 2020-01-08 | 에스케이하이닉스 주식회사 | 반도체 장치 및 그 제조방법, 그리고 반도체 장치를 포함하는 마이크로프로세서, 프로세서, 시스템, 데이터 저장 시스템 및 메모리 시스템 |
Family Cites Families (33)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4173766A (en) | 1977-09-16 | 1979-11-06 | Fairchild Camera And Instrument Corporation | Insulated gate field-effect transistor read-only memory cell |
| US5168334A (en) * | 1987-07-31 | 1992-12-01 | Texas Instruments, Incorporated | Non-volatile semiconductor memory |
| US5284784A (en) | 1991-10-02 | 1994-02-08 | National Semiconductor Corporation | Buried bit-line source-side injection flash memory cell |
| JP3358663B2 (ja) | 1991-10-25 | 2002-12-24 | ローム株式会社 | 半導体記憶装置およびその記憶情報読出方法 |
| US6475846B1 (en) * | 1995-05-18 | 2002-11-05 | Texas Instruments Incorporated | Method of making floating-gate memory-cell array with digital logic transistors |
| US5768192A (en) | 1996-07-23 | 1998-06-16 | Saifun Semiconductors, Ltd. | Non-volatile semiconductor memory cell utilizing asymmetrical charge trapping |
| US5717635A (en) | 1996-08-27 | 1998-02-10 | International Business Machines Corporation | High density EEPROM for solid state file |
| JP3799727B2 (ja) * | 1997-04-08 | 2006-07-19 | 松下電器産業株式会社 | 半導体記憶装置の製造方法 |
| US5966603A (en) | 1997-06-11 | 1999-10-12 | Saifun Semiconductors Ltd. | NROM fabrication method with a periphery portion |
| US6023085A (en) | 1997-12-18 | 2000-02-08 | Advanced Micro Devices, Inc. | Core cell structure and corresponding process for NAND-type high performance flash memory device |
| US6001689A (en) | 1998-01-16 | 1999-12-14 | Advanced Micro Devices, Inc. | Process for fabricating a flash memory with dual function control lines |
| KR100264816B1 (ko) | 1998-03-26 | 2000-09-01 | 윤종용 | 비휘발성 메모리 장치 및 그 동작 방법 |
| US6030871A (en) | 1998-05-05 | 2000-02-29 | Saifun Semiconductors Ltd. | Process for producing two bit ROM cell utilizing angled implant |
| US6153467A (en) | 1998-06-03 | 2000-11-28 | Texas Instruments - Acer Incorporated | Method of fabricating high density buried bit line flash EEPROM memory cell with a shallow trench floating gate |
| US6159795A (en) | 1998-07-02 | 2000-12-12 | Advanced Micro Devices, Inc. | Low voltage junction and high voltage junction optimization for flash memory |
| JP2000031436A (ja) * | 1998-07-09 | 2000-01-28 | Toshiba Corp | 半導体記憶装置およびその製造方法 |
| US6025267A (en) * | 1998-07-15 | 2000-02-15 | Chartered Semiconductor Manufacturing, Ltd. | Silicon nitride--TEOS oxide, salicide blocking layer for deep sub-micron devices |
| US6074915A (en) | 1998-08-17 | 2000-06-13 | Taiwan Semiconductor Manufacturing Company | Method of making embedded flash memory with salicide and sac structure |
| US5972751A (en) | 1998-08-28 | 1999-10-26 | Advanced Micro Devices, Inc. | Methods and arrangements for introducing nitrogen into a tunnel oxide in a non-volatile semiconductor memory device |
| EP0986100B1 (de) * | 1998-09-11 | 2010-05-19 | STMicroelectronics Srl | Elektronisches Bauteil mit EEPROM-Speicherzellen, Hochspannungstransistoren und Niederspannungstransistoren mit Silizidanschlüssen, sowie Herstellungsverfahren desselben |
| US6130453A (en) | 1999-01-04 | 2000-10-10 | International Business Machines Corporation | Flash memory structure with floating gate in vertical trench |
| US6133095A (en) * | 1999-02-04 | 2000-10-17 | Saifun Semiconductors Ltd. | Method for creating diffusion areas for sources and drains without an etch step |
| KR100699608B1 (ko) * | 1999-03-09 | 2007-03-23 | 코닌클리즈케 필립스 일렉트로닉스 엔.브이. | 비휘발성 메모리를 포함하는 반도체 디바이스 |
| TW408450B (en) | 1999-03-29 | 2000-10-11 | United Microelectronics Corp | Manufacture of the flash memory |
| US6143608A (en) | 1999-03-31 | 2000-11-07 | Advanced Micro Devices, Inc. | Barrier layer decreases nitrogen contamination of peripheral gate regions during tunnel oxide nitridation |
| TW415045B (en) * | 1999-08-10 | 2000-12-11 | United Microelectronics Corp | Manufacture of embedded flash memory |
| JP3762584B2 (ja) * | 1999-09-20 | 2006-04-05 | 富士通株式会社 | 半導体集積回路装置 |
| JP4774568B2 (ja) * | 1999-10-01 | 2011-09-14 | ソニー株式会社 | 半導体装置の製造方法 |
| JP2001196549A (ja) * | 2000-01-11 | 2001-07-19 | Mitsubishi Electric Corp | 半導体装置および半導体装置の製造方法 |
| US6372580B1 (en) * | 2000-03-15 | 2002-04-16 | Winbond Electronics Corp. | Process for making mask ROM using a salicide process and mask ROM |
| US6207492B1 (en) * | 2000-06-05 | 2001-03-27 | Taiwan Semiconductor Manufacturing Company | Common gate and salicide word line process for low cost embedded DRAM devices |
| US6306713B1 (en) * | 2000-10-10 | 2001-10-23 | Advanced Micro Devices, Inc. | Method for forming self-aligned contacts and local interconnects for salicided gates using a secondary spacer |
| DE10110150A1 (de) * | 2001-03-02 | 2002-09-19 | Infineon Technologies Ag | Verfahren zum Herstellen von metallischen Bitleitungen für Speicherzellenarrays, Verfahren zum Herstellen von Speicherzellenarrays und Speicherzellenarray |
-
2001
- 2001-10-01 US US09/968,465 patent/US6566194B1/en not_active Expired - Lifetime
-
2002
- 2002-09-27 EP EP02773624A patent/EP1435114B1/de not_active Expired - Fee Related
- 2002-09-27 KR KR10-2004-7004809A patent/KR20040037228A/ko not_active Application Discontinuation
- 2002-09-27 WO PCT/US2002/030784 patent/WO2003030253A2/en active Application Filing
- 2002-09-27 JP JP2003533343A patent/JP5113316B2/ja not_active Expired - Lifetime
- 2002-09-27 CN CNA028190750A patent/CN1610972A/zh active Pending
- 2002-09-27 DE DE60238549T patent/DE60238549D1/de not_active Expired - Lifetime
- 2002-09-27 AU AU2002337732A patent/AU2002337732A1/en not_active Abandoned
- 2002-10-01 TW TW091122597A patent/TW561532B/zh not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| US6566194B1 (en) | 2003-05-20 |
| TW561532B (en) | 2003-11-11 |
| CN1610972A (zh) | 2005-04-27 |
| WO2003030253A3 (en) | 2003-08-28 |
| AU2002337732A1 (en) | 2003-04-14 |
| WO2003030253A2 (en) | 2003-04-10 |
| US20030085417A1 (en) | 2003-05-08 |
| KR20040037228A (ko) | 2004-05-04 |
| EP1435114A2 (de) | 2004-07-07 |
| JP5113316B2 (ja) | 2013-01-09 |
| JP2005505922A (ja) | 2005-02-24 |
| EP1435114B1 (de) | 2010-12-08 |
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