JP5085296B2 - 多層配線基板および半導体装置 - Google Patents

多層配線基板および半導体装置 Download PDF

Info

Publication number
JP5085296B2
JP5085296B2 JP2007312137A JP2007312137A JP5085296B2 JP 5085296 B2 JP5085296 B2 JP 5085296B2 JP 2007312137 A JP2007312137 A JP 2007312137A JP 2007312137 A JP2007312137 A JP 2007312137A JP 5085296 B2 JP5085296 B2 JP 5085296B2
Authority
JP
Japan
Prior art keywords
pad
arrangement
wiring
wiring board
connection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2007312137A
Other languages
English (en)
Japanese (ja)
Other versions
JP2009135375A (ja
JP2009135375A5 (enrdf_load_stackoverflow
Inventor
道夫 堀内
安衛 徳武
茂明 菅沼
直幸 小泉
史雅 片桐
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
Original Assignee
Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP2007312137A priority Critical patent/JP5085296B2/ja
Priority to US12/326,371 priority patent/US7786597B2/en
Publication of JP2009135375A publication Critical patent/JP2009135375A/ja
Publication of JP2009135375A5 publication Critical patent/JP2009135375A5/ja
Application granted granted Critical
Publication of JP5085296B2 publication Critical patent/JP5085296B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15172—Fan-out arrangement of the internal vias
    • H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
    • H05K1/0298—Multilayer circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09218—Conductive traces
    • H05K2201/09227—Layout details of a plurality of traces, e.g. escape layout for Ball Grid Array [BGA] mounting
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10674—Flip chip

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Geometry (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Structure Of Printed Boards (AREA)
JP2007312137A 2007-12-03 2007-12-03 多層配線基板および半導体装置 Expired - Fee Related JP5085296B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2007312137A JP5085296B2 (ja) 2007-12-03 2007-12-03 多層配線基板および半導体装置
US12/326,371 US7786597B2 (en) 2007-12-03 2008-12-02 Multilayer wiring board and semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2007312137A JP5085296B2 (ja) 2007-12-03 2007-12-03 多層配線基板および半導体装置

Publications (3)

Publication Number Publication Date
JP2009135375A JP2009135375A (ja) 2009-06-18
JP2009135375A5 JP2009135375A5 (enrdf_load_stackoverflow) 2010-11-04
JP5085296B2 true JP5085296B2 (ja) 2012-11-28

Family

ID=40720800

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007312137A Expired - Fee Related JP5085296B2 (ja) 2007-12-03 2007-12-03 多層配線基板および半導体装置

Country Status (2)

Country Link
US (1) US7786597B2 (enrdf_load_stackoverflow)
JP (1) JP5085296B2 (enrdf_load_stackoverflow)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101361451B1 (ko) 2009-04-28 2014-02-10 미쓰이 가가쿠 가부시키가이샤 다가 페놀을 제조하는 방법
US9059187B2 (en) 2010-09-30 2015-06-16 Ibiden Co., Ltd. Electronic component having encapsulated wiring board and method for manufacturing the same
CN102097333B (zh) * 2010-11-01 2012-10-17 华为终端有限公司 电路板设计方法、电路板及电子设备
CN103187390B (zh) * 2011-12-31 2016-04-13 中芯国际集成电路制造(北京)有限公司 具有改进排布方式的通孔阵列和具有该阵列的半导体器件
US9872397B2 (en) * 2012-12-05 2018-01-16 Intel Corporation Symmetrical hexagonal-based ball grid array pattern

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3380151B2 (ja) * 1997-12-22 2003-02-24 新光電気工業株式会社 多層回路基板
JP2001015637A (ja) * 1999-06-30 2001-01-19 Mitsubishi Electric Corp 回路配線方式及び回路配線方法及び半導体パッケージ及び半導体パッケージ基板
JP3610262B2 (ja) * 1999-07-22 2005-01-12 新光電気工業株式会社 多層回路基板及び半導体装置
US20050040539A1 (en) * 2002-01-31 2005-02-24 Carlsgaard Eric Stephen Flip chip die bond pads, die bond pad placement and routing optimization
SG107595A1 (en) * 2002-06-18 2004-12-29 Micron Technology Inc Semiconductor devices and semiconductor device components with peripherally located, castellated contacts, assembles and packages including such semiconductor devices or packages and associated methods
JP3780996B2 (ja) * 2002-10-11 2006-05-31 セイコーエプソン株式会社 回路基板、バンプ付き半導体素子の実装構造、バンプ付き半導体素子の実装方法、電気光学装置、並びに電子機器
DE102004047753B4 (de) * 2004-09-30 2009-01-02 Advanced Micro Devices, Inc., Sunnyvale Verbesserte Chip-Kontaktierungsanordnung für Chip-Träger für Flip-Chip-Anwendungen
US7341887B2 (en) * 2004-10-29 2008-03-11 Intel Corporation Integrated circuit die configuration for packaging

Also Published As

Publication number Publication date
JP2009135375A (ja) 2009-06-18
US20090146318A1 (en) 2009-06-11
US7786597B2 (en) 2010-08-31

Similar Documents

Publication Publication Date Title
JP3380151B2 (ja) 多層回路基板
JP2003007750A (ja) 半導体装置
JPWO2009048154A1 (ja) 半導体装置及びその設計方法
JP5085296B2 (ja) 多層配線基板および半導体装置
JPH11150158A (ja) 多層回路基板
JP2009164195A (ja) 半導体チップ
JP3730625B2 (ja) フリップチップボンディングのための有機基板
JP2016033933A (ja) 配線基板
JP2000174153A (ja) 多層配線基板
US8710667B2 (en) Semiconductor device
CN101615605B (zh) 半导体集成电路
US7884478B2 (en) Semiconductor apparatus
US6407460B1 (en) Multilayer circuit board
US7501710B2 (en) Semiconductor integrated circuit and method of manufacturing the same
US8587117B2 (en) Stacked semiconductor chips having circuit element provided with each of the semiconductor chips
JP4429760B2 (ja) 多層配線基板
US20080251286A1 (en) Method For Increasing a Routing Density For a Circuit Board and Such a Circuit Board
JP4708865B2 (ja) 半導体装置
JPH11297885A (ja) 多層回路基板
JP2014003174A (ja) Ｂｇａパッケージ
JP4397628B2 (ja) 印刷回路配線板の配線レイアウト構造
US20110074042A1 (en) Electronic device
JPH11260955A (ja) 多層回路基板
JP2008270319A (ja) 半導体装置
JP2017026927A (ja) プリント配線板

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20100916

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20100916

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20110519

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20120828

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20120905

R150 Certificate of patent or registration of utility model

Ref document number: 5085296

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20150914

Year of fee payment: 3

LAPS Cancellation because of no payment of annual fees