JP5081578B2 - 樹脂封止型半導体装置 - Google Patents
樹脂封止型半導体装置 Download PDFInfo
- Publication number
- JP5081578B2 JP5081578B2 JP2007277269A JP2007277269A JP5081578B2 JP 5081578 B2 JP5081578 B2 JP 5081578B2 JP 2007277269 A JP2007277269 A JP 2007277269A JP 2007277269 A JP2007277269 A JP 2007277269A JP 5081578 B2 JP5081578 B2 JP 5081578B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- resin
- semiconductor chip
- layer
- heat
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W40/00—Arrangements for thermal protection or thermal control
- H10W40/70—Fillings or auxiliary members in containers or in encapsulations for thermal protection or control
- H10W40/77—Auxiliary members characterised by their shape
- H10W40/778—Auxiliary members characterised by their shape in encapsulations
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
- H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
- H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
- H10W74/114—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations
- H10W74/117—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations the substrate having spherical bumps for external connection
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/551—Materials of bond wires
- H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
- H10W72/5522—Materials of bond wires comprising metals or metalloids, e.g. silver comprising gold [Au]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/851—Dispositions of multiple connectors or interconnections
- H10W72/874—On different surfaces
- H10W72/884—Die-attach connectors and bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
- H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
- H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2007277269A JP5081578B2 (ja) | 2007-10-25 | 2007-10-25 | 樹脂封止型半導体装置 |
| US12/256,680 US9484282B2 (en) | 2007-10-25 | 2008-10-23 | Resin-sealed semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2007277269A JP5081578B2 (ja) | 2007-10-25 | 2007-10-25 | 樹脂封止型半導体装置 |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2012190798A Division JP2012256935A (ja) | 2012-08-31 | 2012-08-31 | 樹脂封止型半導体装置 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2009105297A JP2009105297A (ja) | 2009-05-14 |
| JP2009105297A5 JP2009105297A5 (https=) | 2010-12-02 |
| JP5081578B2 true JP5081578B2 (ja) | 2012-11-28 |
Family
ID=40706682
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2007277269A Active JP5081578B2 (ja) | 2007-10-25 | 2007-10-25 | 樹脂封止型半導体装置 |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US9484282B2 (https=) |
| JP (1) | JP5081578B2 (https=) |
Families Citing this family (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5081578B2 (ja) * | 2007-10-25 | 2012-11-28 | ローム株式会社 | 樹脂封止型半導体装置 |
| US8054629B2 (en) * | 2008-09-30 | 2011-11-08 | Intel Corporation | Microfins for cooling an ultramobile device |
| US9355962B2 (en) * | 2009-06-12 | 2016-05-31 | Stats Chippac Ltd. | Integrated circuit package stacking system with redistribution and method of manufacture thereof |
| JP5695306B2 (ja) * | 2009-08-24 | 2015-04-01 | リコー電子デバイス株式会社 | 電子回路部品及びその製造方法 |
| JP5776174B2 (ja) * | 2010-12-15 | 2015-09-09 | 富士通株式会社 | 電子部品内蔵基板の製造方法 |
| US8629567B2 (en) | 2011-12-15 | 2014-01-14 | Stats Chippac Ltd. | Integrated circuit packaging system with contacts and method of manufacture thereof |
| US8623711B2 (en) * | 2011-12-15 | 2014-01-07 | Stats Chippac Ltd. | Integrated circuit packaging system with package-on-package and method of manufacture thereof |
| US9219029B2 (en) | 2011-12-15 | 2015-12-22 | Stats Chippac Ltd. | Integrated circuit packaging system with terminals and method of manufacture thereof |
| JP5945326B2 (ja) * | 2012-07-30 | 2016-07-05 | パナソニック株式会社 | 放熱構造を備えた半導体装置 |
| US9165906B2 (en) * | 2012-12-10 | 2015-10-20 | Invensas Corporation | High performance package on package |
| JP2015012161A (ja) * | 2013-06-28 | 2015-01-19 | 株式会社デンソー | 電子装置 |
| CN103489792B (zh) * | 2013-08-06 | 2016-02-03 | 江苏长电科技股份有限公司 | 先封后蚀三维系统级芯片倒装封装结构及工艺方法 |
| CN103390563B (zh) * | 2013-08-06 | 2016-03-30 | 江苏长电科技股份有限公司 | 先封后蚀芯片倒装三维系统级金属线路板结构及工艺方法 |
| JP6371583B2 (ja) | 2014-05-20 | 2018-08-08 | ローム株式会社 | 半導体パッケージ、pcb基板および半導体装置 |
| US20190214327A1 (en) * | 2018-01-10 | 2019-07-11 | Sonja Koller | Thermal conduction devices and methods for embedded electronic devices |
| CN109698263B (zh) * | 2018-11-28 | 2023-11-03 | 广东晶科电子股份有限公司 | 一种封装基板、半导体器件及其制作方法 |
| CN110767614B (zh) * | 2019-10-10 | 2025-05-02 | 华为技术有限公司 | 封装结构和电子装置 |
| KR102622520B1 (ko) * | 2021-03-11 | 2024-01-08 | 가부시키가이샤 메이코 | 기억 장치 및 기억 장치 모듈 |
| JPWO2024262278A1 (https=) * | 2023-06-22 | 2024-12-26 |
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-
2007
- 2007-10-25 JP JP2007277269A patent/JP5081578B2/ja active Active
-
2008
- 2008-10-23 US US12/256,680 patent/US9484282B2/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| JP2009105297A (ja) | 2009-05-14 |
| US20090184412A1 (en) | 2009-07-23 |
| US9484282B2 (en) | 2016-11-01 |
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