JP5070969B2 - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法 Download PDF

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Publication number
JP5070969B2
JP5070969B2 JP2007189391A JP2007189391A JP5070969B2 JP 5070969 B2 JP5070969 B2 JP 5070969B2 JP 2007189391 A JP2007189391 A JP 2007189391A JP 2007189391 A JP2007189391 A JP 2007189391A JP 5070969 B2 JP5070969 B2 JP 5070969B2
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JP
Japan
Prior art keywords
insulating film
gate electrode
forming
dummy gate
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2007189391A
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English (en)
Japanese (ja)
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JP2009027002A (ja
JP2009027002A5 (enExample
Inventor
智之 平野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP2007189391A priority Critical patent/JP5070969B2/ja
Priority to US12/144,752 priority patent/US7592232B2/en
Publication of JP2009027002A publication Critical patent/JP2009027002A/ja
Publication of JP2009027002A5 publication Critical patent/JP2009027002A5/ja
Application granted granted Critical
Publication of JP5070969B2 publication Critical patent/JP5070969B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/027—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs
    • H10D30/0273—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs forming final gates or dummy gates after forming source and drain electrodes, e.g. contact first technology
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/017—Manufacture or treatment using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/021—Manufacture or treatment using multiple gate spacer layers, e.g. bilayered sidewall spacers
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/954—Making oxide-nitride-oxide device

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
JP2007189391A 2007-07-20 2007-07-20 半導体装置の製造方法 Expired - Fee Related JP5070969B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2007189391A JP5070969B2 (ja) 2007-07-20 2007-07-20 半導体装置の製造方法
US12/144,752 US7592232B2 (en) 2007-07-20 2008-06-24 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2007189391A JP5070969B2 (ja) 2007-07-20 2007-07-20 半導体装置の製造方法

Publications (3)

Publication Number Publication Date
JP2009027002A JP2009027002A (ja) 2009-02-05
JP2009027002A5 JP2009027002A5 (enExample) 2010-04-15
JP5070969B2 true JP5070969B2 (ja) 2012-11-14

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007189391A Expired - Fee Related JP5070969B2 (ja) 2007-07-20 2007-07-20 半導体装置の製造方法

Country Status (2)

Country Link
US (1) US7592232B2 (enExample)
JP (1) JP5070969B2 (enExample)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7932563B2 (en) * 2009-01-30 2011-04-26 Xilinx, Inc. Techniques for improving transistor-to-transistor stress uniformity
DE102009055435B4 (de) * 2009-12-31 2017-11-09 Globalfoundries Dresden Module One Limited Liability Company & Co. Kg Verstärkter Einschluss von Metallgateelektrodenstrukturen mit großem ε durch Verringern der Materialerosion einer dielektrischen Deckschicht beim Erzeugen einer verformungsinduzierenden Halbleiterlegierung
US8981495B2 (en) * 2010-02-08 2015-03-17 Taiwan Semiconductor Manufacturing Company, Ltd. Laterally diffused metal oxide semiconductor transistor with partially unsilicided source/drain
DE102010028460B4 (de) * 2010-04-30 2014-01-23 Globalfoundries Dresden Module One Limited Liability Company & Co. Kg Verfahren zum Herstellen eines Halbleiterbauelements mit einer reduzierten Defektrate in Kontakten, das Austauschgateelektrodenstrukturen unter Anwendung einer Zwischendeckschicht aufweist
US8497210B2 (en) * 2010-10-04 2013-07-30 International Business Machines Corporation Shallow trench isolation chemical mechanical planarization
CN102487014B (zh) * 2010-12-03 2014-03-05 中国科学院微电子研究所 一种半导体结构及其制造方法
CN102487015A (zh) 2010-12-03 2012-06-06 中国科学院微电子研究所 一种半导体结构及其制造方法
CN102938416A (zh) * 2011-08-16 2013-02-20 中国科学院微电子研究所 半导体器件及其制造方法
CN103311294B (zh) * 2012-03-14 2016-09-21 中国科学院微电子研究所 鳍式场效应晶体管及其制造方法
WO2014132537A1 (ja) * 2013-03-01 2014-09-04 日本電気株式会社 情報処理装置、そのデータ処理方法、およびプログラム
KR102065496B1 (ko) * 2013-06-18 2020-01-13 삼성전자주식회사 반도체 장치 및 그 제조 방법
US9449827B2 (en) 2014-02-04 2016-09-20 International Business Machines Corporation Metal semiconductor alloy contact resistance improvement
US9865466B2 (en) * 2015-09-25 2018-01-09 Applied Materials, Inc. Silicide phase control by confinement
US10483167B2 (en) 2017-08-15 2019-11-19 Taiwan Semiconductor Manufacturing Co., Ltd. Method for manufacturing dual FinFET device

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07111962B2 (ja) * 1992-11-27 1995-11-29 日本電気株式会社 選択平坦化ポリッシング方法
JPH1168100A (ja) * 1997-08-19 1999-03-09 Rohm Co Ltd 半導体装置の製造方法
WO2001071807A1 (en) * 2000-03-24 2001-09-27 Fujitsu Limited Semiconductor device and method of manufacture thereof
JP2001308318A (ja) 2000-04-19 2001-11-02 Mitsubishi Electric Corp 半導体装置の製造方法及び半導体装置
JP2002151685A (ja) * 2000-11-14 2002-05-24 Fujitsu Ltd 絶縁ゲート型半導体装置の製造方法
JP3966102B2 (ja) * 2002-07-05 2007-08-29 松下電器産業株式会社 半導体装置の製造方法
JP4107021B2 (ja) 2002-09-10 2008-06-25 ダイソー株式会社 固体塩基触媒、その製造法及びそれを用いるエポキシ化合物の製造法
JP4546201B2 (ja) 2004-03-17 2010-09-15 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
JP2006073704A (ja) * 2004-09-01 2006-03-16 Seiko Epson Corp 半導体装置の製造方法
US7091118B1 (en) * 2004-11-16 2006-08-15 Advanced Micro Devices, Inc. Replacement metal gate transistor with metal-rich silicon layer and method for making the same
JP2007095872A (ja) * 2005-09-28 2007-04-12 Toshiba Corp 半導体装置の製造方法
JP4997752B2 (ja) * 2005-12-13 2012-08-08 ソニー株式会社 半導体装置の製造方法

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Publication number Publication date
US7592232B2 (en) 2009-09-22
JP2009027002A (ja) 2009-02-05
US20090023261A1 (en) 2009-01-22

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