JP5062955B2 - 緩和Ｓｉ１−ｘＧｅｘ層を形成する方法 - Google Patents

緩和Ｓｉ１−ｘＧｅｘ層を形成する方法 Download PDF

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JP5062955B2
JP5062955B2 JP2004553934A JP2004553934A JP5062955B2 JP 5062955 B2 JP5062955 B2 JP 5062955B2 JP 2004553934 A JP2004553934 A JP 2004553934A JP 2004553934 A JP2004553934 A JP 2004553934A JP 5062955 B2 JP5062955 B2 JP 5062955B2
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layer
single crystal
epitaxial
substrate
crystal surface
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JP2006506821A5 (enExample
JP2006506821A (ja
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クリスチャンセン、シルケ、エイチ
チュー、ジャック、オー
グリル、アルフレッド
ムーニー、パトリシア、エム
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International Business Machines Corp
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    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
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    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
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    • H01L21/02373—Group 14 semiconducting materials
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    • H01L21/02367—Substrates
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    • H01L21/02104—Forming layers
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    • H01L21/02518—Deposited layers
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    • H01L21/02532—Silicon, silicon germanium, germanium
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    • H01L21/02104—Forming layers
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    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
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    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
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    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
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    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02694—Controlling the interface between substrate and epitaxial layer, e.g. by ion implantation followed by annealing
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
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    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/933—Germanium or silicon or Ge-Si on III-V

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  • Condensed Matter Physics & Semiconductors (AREA)
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  • High Energy & Nuclear Physics (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Recrystallisation Techniques (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Thin Film Transistor (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
JP2004553934A 2002-11-19 2003-11-19 緩和Ｓｉ１−ｘＧｅｘ層を形成する方法 Expired - Fee Related JP5062955B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10/299,880 US6855649B2 (en) 2001-06-12 2002-11-19 Relaxed SiGe layers on Si or silicon-on-insulator substrates by ion implantation and thermal annealing
US10/299,880 2002-11-19
PCT/US2003/036969 WO2004047150A2 (en) 2002-11-19 2003-11-19 RELAXED SiGe LAYERS ON Si OR SILICON-ON-INSULATOR SUBSTRATES BY ION IMPLANTATION AND THERMAL ANNEALING

Publications (3)

Publication Number Publication Date
JP2006506821A JP2006506821A (ja) 2006-02-23
JP2006506821A5 JP2006506821A5 (enExample) 2006-11-02
JP5062955B2 true JP5062955B2 (ja) 2012-10-31

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US (1) US6855649B2 (enExample)
EP (1) EP1570511A4 (enExample)
JP (1) JP5062955B2 (enExample)
KR (1) KR100724509B1 (enExample)
CN (1) CN100370586C (enExample)
AU (1) AU2003295647A1 (enExample)
WO (1) WO2004047150A2 (enExample)

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KR20050074980A (ko) 2005-07-19
CN1711625A (zh) 2005-12-21
US20030218189A1 (en) 2003-11-27
US6855649B2 (en) 2005-02-15
AU2003295647A8 (en) 2004-06-15
EP1570511A4 (en) 2009-06-10
AU2003295647A1 (en) 2004-06-15
WO2004047150A3 (en) 2004-06-24
WO2004047150A2 (en) 2004-06-03
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