CN100370586C - 通过离子注入和热退火获得的在Si或绝缘体上硅衬底上的弛豫SiGe层 - Google Patents

通过离子注入和热退火获得的在Si或绝缘体上硅衬底上的弛豫SiGe层 Download PDF

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Publication number
CN100370586C
CN100370586C CNB2003801035173A CN200380103517A CN100370586C CN 100370586 C CN100370586 C CN 100370586C CN B2003801035173 A CNB2003801035173 A CN B2003801035173A CN 200380103517 A CN200380103517 A CN 200380103517A CN 100370586 C CN100370586 C CN 100370586C
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layer
crystal
ion
epitaxy
scope
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CN1711625A (zh
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S·H·克里斯坦森
J·O·初
A·格里尔
P·M·穆尼
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Core Usa Second LLC
GlobalFoundries Inc
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International Business Machines Corp
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    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
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    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation
    • H01L21/263Bombardment with radiation with high-energy radiation
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    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
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    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
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    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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    • Y10S438/933Germanium or silicon or Ge-Si on III-V

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  • Recrystallisation Techniques (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Thin Film Transistor (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
CNB2003801035173A 2002-11-19 2003-11-19 通过离子注入和热退火获得的在Si或绝缘体上硅衬底上的弛豫SiGe层 Expired - Fee Related CN100370586C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/299,880 US6855649B2 (en) 2001-06-12 2002-11-19 Relaxed SiGe layers on Si or silicon-on-insulator substrates by ion implantation and thermal annealing
US10/299,880 2002-11-19

Publications (2)

Publication Number Publication Date
CN1711625A CN1711625A (zh) 2005-12-21
CN100370586C true CN100370586C (zh) 2008-02-20

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US (1) US6855649B2 (enExample)
EP (1) EP1570511A4 (enExample)
JP (1) JP5062955B2 (enExample)
KR (1) KR100724509B1 (enExample)
CN (1) CN100370586C (enExample)
AU (1) AU2003295647A1 (enExample)
WO (1) WO2004047150A2 (enExample)

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US9570300B1 (en) 2016-02-08 2017-02-14 International Business Machines Corporation Strain relaxed buffer layers with virtually defect free regions

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