CN100370586C - 通过离子注入和热退火获得的在Si或绝缘体上硅衬底上的弛豫SiGe层 - Google Patents
通过离子注入和热退火获得的在Si或绝缘体上硅衬底上的弛豫SiGe层 Download PDFInfo
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- CN100370586C CN100370586C CNB2003801035173A CN200380103517A CN100370586C CN 100370586 C CN100370586 C CN 100370586C CN B2003801035173 A CNB2003801035173 A CN B2003801035173A CN 200380103517 A CN200380103517 A CN 200380103517A CN 100370586 C CN100370586 C CN 100370586C
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
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- H01L21/02365—Forming inorganic semiconducting materials on a substrate
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- H01L21/02518—Deposited layers
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- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
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- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
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- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/933—Germanium or silicon or Ge-Si on III-V
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Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/299,880 US6855649B2 (en) | 2001-06-12 | 2002-11-19 | Relaxed SiGe layers on Si or silicon-on-insulator substrates by ion implantation and thermal annealing |
| US10/299,880 | 2002-11-19 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1711625A CN1711625A (zh) | 2005-12-21 |
| CN100370586C true CN100370586C (zh) | 2008-02-20 |
Family
ID=32324383
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2003801035173A Expired - Fee Related CN100370586C (zh) | 2002-11-19 | 2003-11-19 | 通过离子注入和热退火获得的在Si或绝缘体上硅衬底上的弛豫SiGe层 |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US6855649B2 (enExample) |
| EP (1) | EP1570511A4 (enExample) |
| JP (1) | JP5062955B2 (enExample) |
| KR (1) | KR100724509B1 (enExample) |
| CN (1) | CN100370586C (enExample) |
| AU (1) | AU2003295647A1 (enExample) |
| WO (1) | WO2004047150A2 (enExample) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101872725B (zh) * | 2009-04-23 | 2013-01-02 | 台湾积体电路制造股份有限公司 | 半导体结构的制造方法与半导体元件 |
| US9570300B1 (en) | 2016-02-08 | 2017-02-14 | International Business Machines Corporation | Strain relaxed buffer layers with virtually defect free regions |
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| US6703688B1 (en) * | 2001-03-02 | 2004-03-09 | Amberwave Systems Corporation | Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits |
| US6830976B2 (en) * | 2001-03-02 | 2004-12-14 | Amberwave Systems Corproation | Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits |
| US6940089B2 (en) | 2001-04-04 | 2005-09-06 | Massachusetts Institute Of Technology | Semiconductor device structure |
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| US20030227057A1 (en) | 2002-06-07 | 2003-12-11 | Lochtefeld Anthony J. | Strained-semiconductor-on-insulator device structures |
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Also Published As
| Publication number | Publication date |
|---|---|
| JP2006506821A (ja) | 2006-02-23 |
| EP1570511A2 (en) | 2005-09-07 |
| KR20050074980A (ko) | 2005-07-19 |
| CN1711625A (zh) | 2005-12-21 |
| US20030218189A1 (en) | 2003-11-27 |
| US6855649B2 (en) | 2005-02-15 |
| AU2003295647A8 (en) | 2004-06-15 |
| JP5062955B2 (ja) | 2012-10-31 |
| EP1570511A4 (en) | 2009-06-10 |
| AU2003295647A1 (en) | 2004-06-15 |
| WO2004047150A3 (en) | 2004-06-24 |
| WO2004047150A2 (en) | 2004-06-03 |
| KR100724509B1 (ko) | 2007-06-04 |
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