KR100724509B1 - 이온 주입 및 열적 어닐링에 의한 실리콘 또는 실리콘 온인슐레이터 기판들 상의 이완된 SiGe층 - Google Patents
이온 주입 및 열적 어닐링에 의한 실리콘 또는 실리콘 온인슐레이터 기판들 상의 이완된 SiGe층 Download PDFInfo
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- KR100724509B1 KR100724509B1 KR1020057007781A KR20057007781A KR100724509B1 KR 100724509 B1 KR100724509 B1 KR 100724509B1 KR 1020057007781 A KR1020057007781 A KR 1020057007781A KR 20057007781 A KR20057007781 A KR 20057007781A KR 100724509 B1 KR100724509 B1 KR 100724509B1
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/02518—Deposited layers
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- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
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- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
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- H01L21/02694—Controlling the interface between substrate and epitaxial layer, e.g. by ion implantation followed by annealing
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
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- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/933—Germanium or silicon or Ge-Si on III-V
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Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/299,880 | 2002-11-19 | ||
| US10/299,880 US6855649B2 (en) | 2001-06-12 | 2002-11-19 | Relaxed SiGe layers on Si or silicon-on-insulator substrates by ion implantation and thermal annealing |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20050074980A KR20050074980A (ko) | 2005-07-19 |
| KR100724509B1 true KR100724509B1 (ko) | 2007-06-04 |
Family
ID=32324383
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020057007781A Expired - Fee Related KR100724509B1 (ko) | 2002-11-19 | 2003-11-19 | 이온 주입 및 열적 어닐링에 의한 실리콘 또는 실리콘 온인슐레이터 기판들 상의 이완된 SiGe층 |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US6855649B2 (enExample) |
| EP (1) | EP1570511A4 (enExample) |
| JP (1) | JP5062955B2 (enExample) |
| KR (1) | KR100724509B1 (enExample) |
| CN (1) | CN100370586C (enExample) |
| AU (1) | AU2003295647A1 (enExample) |
| WO (1) | WO2004047150A2 (enExample) |
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| WO2018012546A1 (ja) * | 2016-07-15 | 2018-01-18 | 国立大学法人東京農工大学 | 半導体積層膜の製造方法、および半導体積層膜 |
| CN111128699B (zh) * | 2019-11-20 | 2022-05-13 | 济南晶正电子科技有限公司 | 一种复合单晶压电衬底薄膜及其制备方法 |
| WO2024263524A1 (en) * | 2023-06-20 | 2024-12-26 | Applied Materials, Inc. | Reduced strain and stop layer for si/sige epi stacks |
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| US6251720B1 (en) * | 1996-09-27 | 2001-06-26 | Randhir P. S. Thakur | High pressure reoxidation/anneal of high dielectric constant materials |
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| DE19859429A1 (de) * | 1998-12-22 | 2000-06-29 | Daimler Chrysler Ag | Verfahren zur Herstellung epitaktischer Silizium-Germaniumschichten |
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| US6995076B2 (en) * | 2000-09-05 | 2006-02-07 | The Regents Of The University Of California | Relaxed SiGe films by surfactant mediation |
| US6593625B2 (en) * | 2001-06-12 | 2003-07-15 | International Business Machines Corporation | Relaxed SiGe layers on Si or silicon-on-insulator substrates by ion implantation and thermal annealing |
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| JP2004079912A (ja) * | 2002-08-21 | 2004-03-11 | Sharp Corp | 半導体基板改質方法およびこの方法を用いた半導体装置 |
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| KR20050003992A (ko) * | 2003-07-01 | 2005-01-12 | 인터내셔널 비지네스 머신즈 코포레이션 | 실리콘 산화에 의한 결함 감소 |
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| CN100370586C (zh) | 2008-02-20 |
| US6855649B2 (en) | 2005-02-15 |
| JP5062955B2 (ja) | 2012-10-31 |
| KR20050074980A (ko) | 2005-07-19 |
| CN1711625A (zh) | 2005-12-21 |
| JP2006506821A (ja) | 2006-02-23 |
| US20030218189A1 (en) | 2003-11-27 |
| WO2004047150A3 (en) | 2004-06-24 |
| AU2003295647A8 (en) | 2004-06-15 |
| EP1570511A2 (en) | 2005-09-07 |
| EP1570511A4 (en) | 2009-06-10 |
| WO2004047150A2 (en) | 2004-06-03 |
| AU2003295647A1 (en) | 2004-06-15 |
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