JP5010815B2 - ゲートリセス構造及びその形成方法 - Google Patents
ゲートリセス構造及びその形成方法 Download PDFInfo
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- JP5010815B2 JP5010815B2 JP2005199719A JP2005199719A JP5010815B2 JP 5010815 B2 JP5010815 B2 JP 5010815B2 JP 2005199719 A JP2005199719 A JP 2005199719A JP 2005199719 A JP2005199719 A JP 2005199719A JP 5010815 B2 JP5010815 B2 JP 5010815B2
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- 238000000034 method Methods 0.000 title claims description 37
- 239000000758 substrate Substances 0.000 claims description 57
- 238000002955 isolation Methods 0.000 claims description 42
- 150000002500 ions Chemical class 0.000 claims description 29
- 238000003860 storage Methods 0.000 claims description 27
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 20
- 229910052710 silicon Inorganic materials 0.000 claims description 20
- 239000010703 silicon Substances 0.000 claims description 20
- 238000005530 etching Methods 0.000 claims description 15
- 238000005468 ion implantation Methods 0.000 claims description 12
- 125000006850 spacer group Chemical group 0.000 claims description 6
- 239000012535 impurity Substances 0.000 claims description 4
- 238000000638 solvent extraction Methods 0.000 claims description 2
- 230000015572 biosynthetic process Effects 0.000 description 23
- 230000008569 process Effects 0.000 description 15
- 230000005684 electric field Effects 0.000 description 7
- 150000004767 nitrides Chemical class 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 230000004888 barrier function Effects 0.000 description 3
- 238000009826 distribution Methods 0.000 description 3
- 239000004020 conductor Substances 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/1037—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure and non-planar channel
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
- H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/05—Making the transistor
- H10B12/053—Making the transistor the transistor being at least partially in a trench in the substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Semiconductor Memories (AREA)
- Element Separation (AREA)
Description
Claims (10)
- 活性領域と素子分離領域とに区画されているシリコン基板と、
前記基板上に形成されている複数のゲートと、
前記ゲート側壁に形成されているゲートスペーサーと、
前記ゲート両側の基板内に形成されており、相互にイオン濃度が異なる2つのジャンクションと、を含み、
ゲート下部面が、前記基板の前記活性領域に形成され、前記基板表面に位置する上側下面と、該上側下面よりも低い位置に形成される下側下面と、前記上側下面及び前記下側下面同士の間の垂直面とからなる段付プロファイルを有するものの、前記下側下面は、前記活性領域にのみ位置し、前記素子分離領域には配置されず、かつ、ストレージノード部及びビットラインノード部の上面が、前記ゲートの前記下側下面から外れた基板表面に位置することを特徴とするゲートリセス構造。 - 前記ゲート下部面の前記下側下面と前記上側下面とは、相互に同じ面積を有することを特徴とする請求項1に記載のゲートリセス構造。
- 前記下側下面は、前記上側下面よりも広い面積を有することを特徴とする請求項1に記載のゲートリセス構造。
- 前記ゲート下部面の前記垂直面は、10〜90゜の傾斜角を有することを特徴とする請求項1に記載のゲートリセス構造。
- 前記ゲート下部面の前記垂直面は、50〜2500Åの高さを有することを特徴とする請求項1に記載のゲートリセス構造。
- シリコン基板を素子分離領域と活性領域とに区画する段階と、
前記シリコン基板の前記活性領域の一部を所定深さにエッチングして、リセスを形成する段階と、
前記シリコン基板に第1次しきい電圧調節イオンを注入する段階と、
前記シリコン基板上に複数のゲートを形成するものの、前記活性領域上に形成するゲートは、前記リセスと一部が重なるように形成する段階と、
前記複数のゲートを有する前記シリコン基板上にストレージノード部は覆い、ビットラインノード部のみを露出させるイオン注入マスクを形成する段階と、
前記イオン注入マスクを用いて第2次しきい電圧調節イオンを注入する段階と、
前記イオン注入マスクを除去する段階と、
前記イオン注入マスクが除去された基板内にジャンクション形成用不純物イオンを注入して、前記ゲート両側の基板内に相互にイオン濃度が異なる2つのジャンクションを形成する段階と、
を含み、
前記シリコン基板上に複数のゲートを形成する段階は、ゲート下部面が、前記基板の前記活性領域に形成され、前記基板表面に位置する上側下面と、該上側下面よりも低い位置に形成される下側下面と、前記上側下面及び前記下側下面同士の間の垂直面とからなる段付プロファイルを有するものの、前記下側下面は、前記活性領域にのみ位置し、前記素子分離領域には配置されず、かつ、前記ストレージノード部及び前記ビットラインノード部の上面が、前記ゲートの前記下側下面から外れた基板表面に位置するように形成する段階を含むことを特徴とするゲートリセス構造の形成方法。 - 前記ゲート下部面の前記下側下面と前記上側下面とは、相互に同じ面積を有することを特徴とする請求項6に記載のゲートリセス構造の形成方法。
- 前記下側下面は、前記上側下面よりも広い面積を有することを特徴とする請求項6に記載のゲートリセス構造の形成方法。
- 前記ゲート下部面の前記垂直面は、10〜90゜の傾斜角を有することを特徴とする請求項6に記載のゲートリセス構造の形成方法。
- 前記ゲート下部面の前記垂直面は、50〜2500Åの高さを有することを特徴とする請求項6に記載のゲートリセス構造の形成方法。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020040101388A KR100564434B1 (ko) | 2004-12-03 | 2004-12-03 | 리세스 게이트 및 그 제조 방법 |
KR10-2004-0101388 | 2004-12-03 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2006165504A JP2006165504A (ja) | 2006-06-22 |
JP5010815B2 true JP5010815B2 (ja) | 2012-08-29 |
Family
ID=36573228
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2005199719A Expired - Fee Related JP5010815B2 (ja) | 2004-12-03 | 2005-07-08 | ゲートリセス構造及びその形成方法 |
Country Status (4)
Country | Link |
---|---|
US (2) | US7423318B2 (ja) |
JP (1) | JP5010815B2 (ja) |
KR (1) | KR100564434B1 (ja) |
TW (1) | TWI293772B (ja) |
Families Citing this family (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7306552B2 (en) * | 2004-12-03 | 2007-12-11 | Samsung Electronics Co., Ltd. | Semiconductor device having load resistor and method of fabricating the same |
KR100755058B1 (ko) * | 2005-04-04 | 2007-09-06 | 주식회사 하이닉스반도체 | 스텝게이트를 갖는 반도체소자 및 그 제조방법 |
KR100636680B1 (ko) * | 2005-06-29 | 2006-10-23 | 주식회사 하이닉스반도체 | 리세스 게이트 및 비대칭 불순물영역을 갖는 반도체소자 및그 제조방법 |
KR100642384B1 (ko) * | 2005-09-15 | 2006-11-03 | 주식회사 하이닉스반도체 | 반도체 메모리소자의 트랜지스터 및 그 제조방법 |
KR100935192B1 (ko) * | 2006-08-25 | 2010-01-06 | 주식회사 하이닉스반도체 | 모스펫 소자 및 그 제조방법 |
KR100905776B1 (ko) * | 2006-08-25 | 2009-07-02 | 주식회사 하이닉스반도체 | 반도체 소자의 제조방법 |
KR100826650B1 (ko) * | 2006-12-28 | 2008-05-06 | 주식회사 하이닉스반도체 | 변형된 리세스채널 게이트를 갖는 반도체소자 및 그제조방법 |
KR100826981B1 (ko) | 2006-12-28 | 2008-05-02 | 주식회사 하이닉스반도체 | 반도체 소자 및 그의 제조 방법 |
KR100843855B1 (ko) * | 2007-01-18 | 2008-07-03 | 주식회사 하이닉스반도체 | 반도체 소자 및 그의 제조 방법 |
KR100869351B1 (ko) | 2007-06-28 | 2008-11-19 | 주식회사 하이닉스반도체 | 반도체 소자의 제조방법 |
KR101024734B1 (ko) * | 2008-10-06 | 2011-03-24 | 주식회사 하이닉스반도체 | 반도체 소자 및 그 제조 방법 |
KR101087779B1 (ko) | 2009-09-16 | 2011-11-30 | 주식회사 하이닉스반도체 | 반도체 소자 및 그 형성방법 |
KR101096226B1 (ko) * | 2010-10-28 | 2011-12-22 | 주식회사 하이닉스반도체 | 매립게이트를 구비한 반도체장치 제조 방법 |
KR101725446B1 (ko) * | 2011-08-24 | 2017-04-12 | 삼성전자주식회사 | 반도체 장치 및 그 제조 방법 |
DE102017108738B4 (de) * | 2017-04-24 | 2022-01-27 | Infineon Technologies Ag | SiC-HALBLEITERVORRICHTUNG MIT EINEM VERSATZ IN EINEM GRABENBODEN UND HERSTELLUNGSVERFAHREN HIERFÜR |
US20230140124A1 (en) * | 2021-11-04 | 2023-05-04 | Changxin Memory Technologies, Inc. | Semiconductor structure and manufacturing method thereof |
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US5064777A (en) * | 1990-06-28 | 1991-11-12 | International Business Machines Corporation | Fabrication method for a double trench memory cell device |
JP3716505B2 (ja) * | 1996-08-08 | 2005-11-16 | 富士通株式会社 | 半導体装置及びその製造方法 |
US6051860A (en) * | 1998-01-16 | 2000-04-18 | Matsushita Electric Industrial Co., Ltd. | Nonvolatile semiconductor memory device and method for fabricating the same and semiconductor integrated circuit |
JP2000236074A (ja) * | 1998-12-17 | 2000-08-29 | Hitachi Ltd | 半導体集積回路装置およびその製造方法 |
US6190971B1 (en) * | 1999-05-13 | 2001-02-20 | International Business Machines Corporation | Formation of 5F2 cell with partially vertical transistor and gate conductor aligned buried strap with raised shallow trench isolation region |
JP2000353792A (ja) * | 1999-06-09 | 2000-12-19 | Sanyo Electric Co Ltd | 半導体装置とその製造方法 |
KR100307531B1 (ko) * | 1999-08-09 | 2001-11-01 | 김영환 | 모스페트 소자와 이를 이용한 메모리셀 및 그 제조 방법 |
DE19954867C1 (de) * | 1999-11-15 | 2000-12-07 | Infineon Technologies Ag | DRAM-Zellenanordnung und Verfahren zu deren Herstellung |
KR100351055B1 (ko) * | 2000-06-27 | 2002-09-05 | 삼성전자 주식회사 | 채널 이온 주입용 마스크 패턴을 이용한 반도체 메모리소자의 제조 방법 |
US6720630B2 (en) | 2001-05-30 | 2004-04-13 | International Business Machines Corporation | Structure and method for MOSFET with metallic gate electrode |
US6686637B1 (en) | 2002-11-21 | 2004-02-03 | International Business Machines Corporation | Gate structure with independently tailored vertical doping profile |
KR100549950B1 (ko) * | 2003-12-23 | 2006-02-07 | 삼성전자주식회사 | 리세스 타입 모오스 트랜지스터의 제조방법 및 그의 구조 |
JP2005236135A (ja) * | 2004-02-20 | 2005-09-02 | Elpida Memory Inc | 半導体装置の製造方法 |
KR100549578B1 (ko) * | 2004-05-25 | 2006-02-08 | 주식회사 하이닉스반도체 | Mos 트랜지스터 제조 방법 |
DE102004063025B4 (de) * | 2004-07-27 | 2010-07-29 | Hynix Semiconductor Inc., Icheon | Speicherbauelement und Verfahren zur Herstellung desselben |
-
2004
- 2004-12-03 KR KR1020040101388A patent/KR100564434B1/ko active IP Right Grant
-
2005
- 2005-06-14 US US11/152,575 patent/US7423318B2/en active Active
- 2005-06-16 TW TW094119992A patent/TWI293772B/zh not_active IP Right Cessation
- 2005-07-08 JP JP2005199719A patent/JP5010815B2/ja not_active Expired - Fee Related
-
2008
- 2008-08-08 US US12/188,756 patent/US7622353B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
TWI293772B (en) | 2008-02-21 |
US20090004798A1 (en) | 2009-01-01 |
US7423318B2 (en) | 2008-09-09 |
KR100564434B1 (ko) | 2006-03-28 |
US7622353B2 (en) | 2009-11-24 |
TW200620390A (en) | 2006-06-16 |
US20060118889A1 (en) | 2006-06-08 |
JP2006165504A (ja) | 2006-06-22 |
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