JP4951202B2 - シリコンオンインシュレータ構造の製造方法 - Google Patents

シリコンオンインシュレータ構造の製造方法 Download PDF

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JP4951202B2
JP4951202B2 JP2004504268A JP2004504268A JP4951202B2 JP 4951202 B2 JP4951202 B2 JP 4951202B2 JP 2004504268 A JP2004504268 A JP 2004504268A JP 2004504268 A JP2004504268 A JP 2004504268A JP 4951202 B2 JP4951202 B2 JP 4951202B2
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layer
semiconductor
epitaxial
insulator
insulator layer
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JP2005524987A5 (enExample
JP2005524987A (ja
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クリス ワークホウブン
イボ ラアイマケルス
チャンタル アレナ
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エーエスエム アメリカ インコーポレイテッド
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
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    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
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    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
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    • H01L21/76262Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using selective deposition of single crystal silicon, i.e. SEG techniques
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    • H01L21/02263Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
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    • H01L21/02612Formation types
    • H01L21/02617Deposition types
    • H01L21/0262Reduction or decomposition of gaseous compounds, e.g. CVD

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Recrystallisation Techniques (AREA)
  • Thin Film Transistor (AREA)
  • Formation Of Insulating Films (AREA)
  • Chemical Vapour Deposition (AREA)
JP2004504268A 2002-05-07 2003-05-07 シリコンオンインシュレータ構造の製造方法 Expired - Lifetime JP4951202B2 (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US37886802P 2002-05-07 2002-05-07
US60/378,868 2002-05-07
US45501803P 2003-03-12 2003-03-12
US60/455,018 2003-03-12
PCT/US2003/014314 WO2003096385A2 (en) 2002-05-07 2003-05-07 Silicon-on-insulator structures and methods

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JP2005524987A JP2005524987A (ja) 2005-08-18
JP2005524987A5 JP2005524987A5 (enExample) 2006-06-22
JP4951202B2 true JP4951202B2 (ja) 2012-06-13

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US (1) US7452757B2 (enExample)
EP (1) EP1502285A2 (enExample)
JP (1) JP4951202B2 (enExample)
KR (1) KR101023034B1 (enExample)
WO (1) WO2003096385A2 (enExample)

Families Citing this family (42)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7192888B1 (en) * 2000-08-21 2007-03-20 Micron Technology, Inc. Low selectivity deposition methods
US6921702B2 (en) 2002-07-30 2005-07-26 Micron Technology Inc. Atomic layer deposited nanolaminates of HfO2/ZrO2 films as gate dielectrics
US7682947B2 (en) * 2003-03-13 2010-03-23 Asm America, Inc. Epitaxial semiconductor deposition methods and structures
US7238595B2 (en) * 2003-03-13 2007-07-03 Asm America, Inc. Epitaxial semiconductor deposition methods and structures
KR20060056331A (ko) * 2003-07-23 2006-05-24 에이에스엠 아메리카, 인코포레이티드 절연체-상-실리콘 구조 및 벌크 기판 상의 SiGe 증착
WO2005013326A2 (en) * 2003-07-30 2005-02-10 Asm America, Inc. Epitaxial growth of relaxed silicon germanium layers
US7601649B2 (en) 2004-08-02 2009-10-13 Micron Technology, Inc. Zirconium-doped tantalum oxide films
US7081421B2 (en) 2004-08-26 2006-07-25 Micron Technology, Inc. Lanthanide oxide dielectric layer
US7235501B2 (en) 2004-12-13 2007-06-26 Micron Technology, Inc. Lanthanum hafnium oxide dielectrics
US7662729B2 (en) 2005-04-28 2010-02-16 Micron Technology, Inc. Atomic layer deposition of a ruthenium layer to a lanthanide oxide dielectric layer
KR100676201B1 (ko) * 2005-05-24 2007-01-30 삼성전자주식회사 원자층 적층법을 이용한 반도체 디바이스 제조방법
US7572695B2 (en) 2005-05-27 2009-08-11 Micron Technology, Inc. Hafnium titanium oxide films
JP2006344865A (ja) * 2005-06-10 2006-12-21 Toyoko Kagaku Co Ltd Soi基板及び該基板の製造方法
US7972974B2 (en) 2006-01-10 2011-07-05 Micron Technology, Inc. Gallium lanthanide oxide films
US7901968B2 (en) * 2006-03-23 2011-03-08 Asm America, Inc. Heteroepitaxial deposition over an oxidized surface
KR100774818B1 (ko) * 2006-08-22 2007-11-07 동부일렉트로닉스 주식회사 Soi기판
EP1975988B1 (en) * 2007-03-28 2015-02-25 Siltronic AG Multilayered semiconductor wafer and process for its production
JP5496540B2 (ja) * 2008-04-24 2014-05-21 株式会社半導体エネルギー研究所 半導体基板の作製方法
US8765508B2 (en) 2008-08-27 2014-07-01 Soitec Methods of fabricating semiconductor structures or devices using layers of semiconductor material having selected or controlled lattice parameters
WO2011061580A1 (en) 2009-11-18 2011-05-26 S.O.I.Tec Silicon On Insulator Technologies Methods of fabricating semiconductor structures and devices using glass bonding layers, and semiconductor structures and devices formed by such methods
US8592294B2 (en) 2010-02-22 2013-11-26 Asm International N.V. High temperature atomic layer deposition of dielectric oxides
US9608119B2 (en) 2010-03-02 2017-03-28 Micron Technology, Inc. Semiconductor-metal-on-insulator structures, methods of forming such structures, and semiconductor devices including such structures
US8507966B2 (en) 2010-03-02 2013-08-13 Micron Technology, Inc. Semiconductor cells, arrays, devices and systems having a buried conductive line and methods for forming the same
US9646869B2 (en) 2010-03-02 2017-05-09 Micron Technology, Inc. Semiconductor devices including a diode structure over a conductive strap and methods of forming such semiconductor devices
US8288795B2 (en) 2010-03-02 2012-10-16 Micron Technology, Inc. Thyristor based memory cells, devices and systems including the same and methods for forming the same
DE102010035489A1 (de) * 2010-08-26 2012-03-01 Osram Opto Semiconductors Gmbh Halbleiterbauelement und Verfahren zur Herstellung eines Halbleiterbauelement
US9023721B2 (en) 2010-11-23 2015-05-05 Soitec Methods of forming bulk III-nitride materials on metal-nitride growth template layers, and structures formed by such methods
FR2968830B1 (fr) 2010-12-08 2014-03-21 Soitec Silicon On Insulator Couches matricielles ameliorees pour le depot heteroepitaxial de materiaux semiconducteurs de nitrure iii en utilisant des procedes hvpe
FR2968678B1 (fr) 2010-12-08 2015-11-20 Soitec Silicon On Insulator Procédés pour former des matériaux a base de nitrure du groupe iii et structures formées par ces procédés
US8753942B2 (en) 2010-12-01 2014-06-17 Intel Corporation Silicon and silicon germanium nanowire structures
US8952418B2 (en) 2011-03-01 2015-02-10 Micron Technology, Inc. Gated bipolar junction transistors
US8519431B2 (en) 2011-03-08 2013-08-27 Micron Technology, Inc. Thyristors
JP5802436B2 (ja) * 2011-05-30 2015-10-28 信越半導体株式会社 貼り合わせウェーハの製造方法
US9105469B2 (en) 2011-06-30 2015-08-11 Piquant Research Llc Defect mitigation structures for semiconductor devices
US9127345B2 (en) 2012-03-06 2015-09-08 Asm America, Inc. Methods for depositing an epitaxial silicon germanium layer having a germanium to silicon ratio greater than 1:1 using silylgermane and a diluent
US9171715B2 (en) 2012-09-05 2015-10-27 Asm Ip Holding B.V. Atomic layer deposition of GeO2
CN102916039B (zh) * 2012-10-19 2016-01-20 清华大学 具有氧化铍的半导体结构
US9218963B2 (en) 2013-12-19 2015-12-22 Asm Ip Holding B.V. Cyclical deposition of germanium
WO2017019096A1 (en) * 2015-07-30 2017-02-02 Halliburton Energy Services, Inc. Integrated computational elements incorporating a stress relief layer
KR102514785B1 (ko) * 2017-05-19 2023-03-29 상라오 징코 솔라 테크놀러지 디벨롭먼트 컴퍼니, 리미티드 태양 전지 및 이의 제조 방법
US12006570B2 (en) * 2017-08-31 2024-06-11 Uchicago Argonne, Llc Atomic layer deposition for continuous, high-speed thin films
KR102871969B1 (ko) 2024-05-14 2025-10-15 연세대학교 산학협력단 결정성 채널층을 포함하는 반도체 소자 및 이의 제조방법

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4199773A (en) * 1978-08-29 1980-04-22 Rca Corporation Insulated gate field effect silicon-on-sapphire transistor and method of making same
JPS60202952A (ja) * 1984-03-28 1985-10-14 Fujitsu Ltd 半導体装置の製造方法
JPH0618174B2 (ja) * 1986-07-08 1994-03-09 シャープ株式会社 半導体基板
JPS63305529A (ja) * 1987-06-05 1988-12-13 Nippon Telegr & Teleph Corp <Ntt> 基板およびその製造方法
JPS6436046A (en) * 1987-07-31 1989-02-07 Seiko Epson Corp Manufacture of semiconductor device
US4935382A (en) * 1987-10-30 1990-06-19 American Telephone And Telegraph Company Method of making a semiconductor-insulator-semiconductor structure
US5256550A (en) * 1988-11-29 1993-10-26 Hewlett-Packard Company Fabricating a semiconductor device with strained Si1-x Gex layer
US5310696A (en) * 1989-06-16 1994-05-10 Massachusetts Institute Of Technology Chemical method for the modification of a substrate surface to accomplish heteroepitaxial crystal growth
JPH03109299A (ja) * 1989-09-22 1991-05-09 Nippon Telegr & Teleph Corp <Ntt> 多結晶シリコン膜の形成方法
US5164359A (en) * 1990-04-20 1992-11-17 Eaton Corporation Monolithic integrated circuit having compound semiconductor layer epitaxially grown on ceramic substrate
EP0568064B1 (en) * 1992-05-01 1999-07-14 Texas Instruments Incorporated Pb/Bi-containing high-dielectric constant oxides using a non-Pb/Bi-containing perovskite as a buffer layer
US5478653A (en) * 1994-04-04 1995-12-26 Guenzer; Charles S. Bismuth titanate as a template layer for growth of crystallographically oriented silicon
JPH10144607A (ja) * 1996-11-13 1998-05-29 Hitachi Ltd 半導体基板およびその製造方法ならびにそれを用いた半導体装置およびその製造方法
JPH10265948A (ja) * 1997-03-25 1998-10-06 Rohm Co Ltd 半導体装置用基板およびその製法
CA2232796C (en) * 1997-03-26 2002-01-22 Canon Kabushiki Kaisha Thin film forming process
JPH11233440A (ja) * 1998-02-13 1999-08-27 Toshiba Corp 半導体装置
JP4439020B2 (ja) * 1998-03-26 2010-03-24 株式会社東芝 半導体記憶装置及びその製造方法
US6346732B1 (en) * 1999-05-14 2002-02-12 Kabushiki Kaisha Toshiba Semiconductor device with oxide mediated epitaxial layer
JP2001102555A (ja) * 1999-09-30 2001-04-13 Seiko Epson Corp 半導体装置、薄膜トランジスタ及びそれらの製造方法
US6437375B1 (en) * 2000-06-05 2002-08-20 Micron Technology, Inc. PD-SOI substrate with suppressed floating body effect and method for its fabrication
US6583034B2 (en) * 2000-11-22 2003-06-24 Motorola, Inc. Semiconductor structure including a compliant substrate having a graded monocrystalline layer and methods for fabricating the structure and semiconductor devices including the structure
US6933566B2 (en) * 2001-07-05 2005-08-23 International Business Machines Corporation Method of forming lattice-matched structure on silicon and structure formed thereby
US6693298B2 (en) * 2001-07-20 2004-02-17 Motorola, Inc. Structure and method for fabricating epitaxial semiconductor on insulator (SOI) structures and devices utilizing the formation of a compliant substrate for materials used to form same
US6515335B1 (en) * 2002-01-04 2003-02-04 International Business Machines Corporation Method for fabrication of relaxed SiGe buffer layers on silicon-on-insulators and structures containing the same

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KR20050007472A (ko) 2005-01-18
US7452757B2 (en) 2008-11-18
US20040097022A1 (en) 2004-05-20
KR101023034B1 (ko) 2011-03-24
WO2003096385A3 (en) 2004-07-29
WO2003096385A2 (en) 2003-11-20
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