JP4950888B2 - プラズマ処理を用いて高誘電率層を有するゲート誘電体積層体を改善する方法 - Google Patents

プラズマ処理を用いて高誘電率層を有するゲート誘電体積層体を改善する方法 Download PDF

Info

Publication number
JP4950888B2
JP4950888B2 JP2007527883A JP2007527883A JP4950888B2 JP 4950888 B2 JP4950888 B2 JP 4950888B2 JP 2007527883 A JP2007527883 A JP 2007527883A JP 2007527883 A JP2007527883 A JP 2007527883A JP 4950888 B2 JP4950888 B2 JP 4950888B2
Authority
JP
Japan
Prior art keywords
plasma
gate dielectric
amount
gas
radicals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2007527883A
Other languages
English (en)
Japanese (ja)
Other versions
JP2008510319A (ja
JP2008510319A5 (enExample
Inventor
寛明 新実
コロンボ，ルイジ
晃司 下村
卓也 菅原
龍夫 松土
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Publication of JP2008510319A publication Critical patent/JP2008510319A/ja
Publication of JP2008510319A5 publication Critical patent/JP2008510319A5/ja
Application granted granted Critical
Publication of JP4950888B2 publication Critical patent/JP4950888B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02142—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing silicon and at least one metal element, e.g. metal silicate based insulators or metal silicon oxynitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/022—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28185—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28202—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/3115—Doping the insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/691—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator comprising metallic compounds, e.g. metal oxides or metal silicates 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/681—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered
    • H10D64/685—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered being perpendicular to the channel plane

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Chemical & Material Sciences (AREA)
  • Plasma & Fusion (AREA)
  • Formation Of Insulating Films (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
JP2007527883A 2004-08-18 2005-08-11 プラズマ処理を用いて高誘電率層を有するゲート誘電体積層体を改善する方法 Expired - Fee Related JP4950888B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10/920,990 2004-08-18
US10/920,990 US7163877B2 (en) 2004-08-18 2004-08-18 Method and system for modifying a gate dielectric stack containing a high-k layer using plasma processing
PCT/US2005/028610 WO2006023373A1 (en) 2004-08-18 2005-08-11 A method and system for modifying a gate dielectric stack containing a high-k layer using plasma processing

Publications (3)

Publication Number Publication Date
JP2008510319A JP2008510319A (ja) 2008-04-03
JP2008510319A5 JP2008510319A5 (enExample) 2008-09-25
JP4950888B2 true JP4950888B2 (ja) 2012-06-13

Family

ID=35431477

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007527883A Expired - Fee Related JP4950888B2 (ja) 2004-08-18 2005-08-11 プラズマ処理を用いて高誘電率層を有するゲート誘電体積層体を改善する方法

Country Status (6)

Country Link
US (1) US7163877B2 (enExample)
JP (1) JP4950888B2 (enExample)
KR (1) KR101163264B1 (enExample)
CN (1) CN100568462C (enExample)
TW (1) TWI268553B (enExample)
WO (1) WO2006023373A1 (enExample)

Families Citing this family (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1722406A1 (en) * 2004-03-03 2006-11-15 Tokyo Electron Limited Plasma processing method and computer storing medium
US20070049048A1 (en) * 2005-08-31 2007-03-01 Shahid Rauf Method and apparatus for improving nitrogen profile during plasma nitridation
WO2007133759A2 (en) 2006-05-13 2007-11-22 Tensys Medical, Inc. Continuous positioning apparatus and methods
WO2007132884A1 (ja) * 2006-05-17 2007-11-22 Hitachi Kokusai Electric Inc. 半導体装置の製造方法および基板処理装置
WO2009048602A1 (en) 2007-10-12 2009-04-16 Tensys Medical, Inc. Apparatus and methods for non-invasively measuring a patient's arterial blood pressure
US7964515B2 (en) * 2007-12-21 2011-06-21 Tokyo Electron Limited Method of forming high-dielectric constant films for semiconductor devices
US20090233430A1 (en) * 2008-02-19 2009-09-17 Hitachi-Kokusai Electric In. Semiconductor device manufacturing method, semiconductor device manufacturing apparatus, and semiconductor device manufacturing system
US20100044804A1 (en) * 2008-08-25 2010-02-25 Taiwan Semiconductor Manufacturing Company, Ltd. Novel high-k metal gate structure and method of making
US8193586B2 (en) 2008-08-25 2012-06-05 Taiwan Semiconductor Manufacturing Company, Ltd. Sealing structure for high-K metal gate
US8252653B2 (en) 2008-10-21 2012-08-28 Applied Materials, Inc. Method of forming a non-volatile memory having a silicon nitride charge trap layer
US8198671B2 (en) * 2009-04-22 2012-06-12 Applied Materials, Inc. Modification of charge trap silicon nitride with oxygen plasma
US8962454B2 (en) * 2010-11-04 2015-02-24 Tokyo Electron Limited Method of depositing dielectric films using microwave plasma
WO2012112187A1 (en) * 2011-02-15 2012-08-23 Applied Materials, Inc. Method and apparatus for multizone plasma generation
US9655530B2 (en) 2011-04-29 2017-05-23 Tensys Medical, Inc. Apparatus and methods for non-invasively measuring physiologic parameters of one or more subjects
KR101241049B1 (ko) 2011-08-01 2013-03-15 주식회사 플라즈마트 플라즈마 발생 장치 및 플라즈마 발생 방법
KR101246191B1 (ko) 2011-10-13 2013-03-21 주식회사 윈텔 플라즈마 장치 및 기판 처리 장치
US8890264B2 (en) * 2012-09-26 2014-11-18 Intel Corporation Non-planar III-V field effect transistors with conformal metal gate electrode and nitrogen doping of gate dielectric interface
US9224644B2 (en) * 2012-12-26 2015-12-29 Intermolecular, Inc. Method to control depth profiles of dopants using a remote plasma source
US9343291B2 (en) * 2013-05-15 2016-05-17 Tokyo Electron Limited Method for forming an interfacial layer on a semiconductor using hydrogen plasma
US9331168B2 (en) 2014-01-17 2016-05-03 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and manufacuturing method of the same
CN104821276B (zh) * 2014-01-30 2018-08-10 中芯国际集成电路制造(上海)有限公司 Mos晶体管的制作方法
JP2018528619A (ja) * 2015-09-18 2018-09-27 東京エレクトロン株式会社 ゲルマニウム含有半導体デバイスおよび形成方法
JP6671166B2 (ja) * 2015-12-15 2020-03-25 東京エレクトロン株式会社 絶縁膜積層体の製造方法
US11152214B2 (en) * 2016-04-20 2021-10-19 International Business Machines Corporation Structures and methods for equivalent oxide thickness scaling on silicon germanium channel or III-V channel of semiconductor device
TWI635539B (zh) * 2017-09-15 2018-09-11 金巨達國際股份有限公司 高介電常數介電層、其製造方法及執行該方法之多功能設備
KR102384865B1 (ko) 2018-01-31 2022-04-08 삼성전자주식회사 반도체 소자 제조 방법
CN108735607A (zh) * 2018-05-25 2018-11-02 中国科学院微电子研究所 基于微波等离子体氧化的凹槽mosfet器件的制造方法
US20210057215A1 (en) * 2019-05-03 2021-02-25 Applied Materials, Inc. Treatments to enhance material structures
US12249511B2 (en) * 2019-05-03 2025-03-11 Applied Materials, Inc. Treatments to improve device performance
US11417517B2 (en) * 2019-05-03 2022-08-16 Applied Materials, Inc. Treatments to enhance material structures
TWI837538B (zh) * 2020-11-06 2024-04-01 美商應用材料股份有限公司 增強材料結構的處理

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05221644A (ja) * 1992-02-13 1993-08-31 Matsushita Electric Ind Co Ltd 酸化タンタル薄膜の製造方法
JP3230901B2 (ja) * 1993-06-22 2001-11-19 株式会社東芝 半導体装置の製造方法及びその製造装置
JPH0964307A (ja) * 1995-08-29 1997-03-07 Hitachi Ltd 酸化物薄膜の熱処理方法
US6709715B1 (en) * 1999-06-17 2004-03-23 Applied Materials Inc. Plasma enhanced chemical vapor deposition of copolymer of parylene N and comonomers with various double bonds
KR100760078B1 (ko) * 2000-03-13 2007-09-18 다다히로 오미 산화막의 형성 방법, 질화막의 형성 방법, 산질화막의 형성 방법, 산화막의 스퍼터링 방법, 질화막의 스퍼터링 방법, 산질화막의 스퍼터링 방법, 게이트 절연막의 형성 방법
WO2002001622A2 (en) * 2000-06-26 2002-01-03 North Carolina State University Novel non-crystalline oxides for use in microelectronic, optical, and other applications
US6677254B2 (en) 2001-07-23 2004-01-13 Applied Materials, Inc. Processes for making a barrier between a dielectric and a conductor and products produced therefrom
JP4643884B2 (ja) 2002-06-27 2011-03-02 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
KR100493022B1 (ko) * 2002-07-10 2005-06-07 삼성전자주식회사 Ｓｏｎｏｓ 구조를 갖는 불휘발성 메모리 소자의 제조 방법
WO2004030049A2 (en) * 2002-09-27 2004-04-08 Tokyo Electron Limited A method and system for etching high-k dielectric materials
US6730566B2 (en) 2002-10-04 2004-05-04 Texas Instruments Incorporated Method for non-thermally nitrided gate formation for high voltage devices
US6649538B1 (en) * 2002-10-09 2003-11-18 Taiwan Semiconductor Manufacturing Co. Ltd. Method for plasma treating and plasma nitriding gate oxides
US6689675B1 (en) * 2002-10-31 2004-02-10 Intel Corporation Method for making a semiconductor device having a high-k gate dielectric
AU2003291319A1 (en) 2002-11-08 2004-06-03 Aviza Technology, Inc. Nitridation of high-k dielectrics
US6787440B2 (en) 2002-12-10 2004-09-07 Intel Corporation Method for making a semiconductor device having an ultra-thin high-k gate dielectric
JP2004228355A (ja) * 2003-01-23 2004-08-12 Seiko Epson Corp 絶縁膜基板の製造方法、絶縁膜基板の製造装置及び絶縁膜基板並びに電気光学装置の製造方法及び電気光学装置
KR20060054387A (ko) * 2003-08-04 2006-05-22 에이에스엠 아메리카, 인코포레이티드 증착 전 게르마늄 표면 처리 방법
JP4280686B2 (ja) * 2004-06-30 2009-06-17 キヤノン株式会社 処理方法

Also Published As

Publication number Publication date
US20060040483A1 (en) 2006-02-23
US7163877B2 (en) 2007-01-16
TW200618091A (en) 2006-06-01
TWI268553B (en) 2006-12-11
JP2008510319A (ja) 2008-04-03
WO2006023373A1 (en) 2006-03-02
CN101006566A (zh) 2007-07-25
CN100568462C (zh) 2009-12-09
KR20080009675A (ko) 2008-01-29
KR101163264B1 (ko) 2012-07-05

Similar Documents

Publication Publication Date Title
JP4950888B2 (ja) プラズマ処理を用いて高誘電率層を有するゲート誘電体積層体を改善する方法
US10522343B2 (en) Method of enhancing high-k film nucleation rate and electrical mobility in a semiconductor device by microwave plasma treatment
US8021987B2 (en) Method of modifying insulating film
KR101411744B1 (ko) 하프늄 함유층의 에칭 방법 및 플라즈마 처리 시스템
US7226874B2 (en) Substrate processing method
KR101161468B1 (ko) 반도체 디바이스의 게이트 스택 처리 방법 및 반도체 디바이스의 게이트 스택 처리 시스템
CN101401194B (zh) 使用低能量等离子体系统制造高介电常数晶体管栅极的方法和装置
TWI423333B (zh) 利用低能量電漿系統製造高介電常數電晶體閘極之方法及設備
US7678710B2 (en) Method and apparatus for fabricating a high dielectric constant transistor gate using a low energy plasma system
US20130149852A1 (en) Method for forming a semiconductor device
US20070209930A1 (en) Apparatus for fabricating a high dielectric constant transistor gate using a low energy plasma system
CN100576464C (zh) 等离子体处理方法
US6746925B1 (en) High-k dielectric bird's beak optimizations using in-situ O2 plasma oxidation
US8501628B2 (en) Differential metal gate etching process
TWI459471B (zh) 使用低能量電漿系統製造高介質常數電晶體閘極的方法與設備
US6780788B2 (en) Methods for improving within-wafer uniformity of gate oxide
US7517812B2 (en) Method and system for forming a nitrided germanium-containing layer using plasma processing
US7517818B2 (en) Method for forming a nitrided germanium-containing layer using plasma processing
JP2008515220A (ja) Ｈｉｇｈ−ｋ層内に形態を形成する方法及びシステム

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20080808

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20080808

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20110628

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20110920

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20111018

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20120117

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20120214

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20120309

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20150316

Year of fee payment: 3

R150 Certificate of patent or registration of utility model

Ref document number: 4950888

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees