TWI268553B - A method and system for modifying a gate dielectric stack containing a high-k layer using plasma processing - Google Patents

A method and system for modifying a gate dielectric stack containing a high-k layer using plasma processing

Info

Publication number
TWI268553B
TWI268553B TW094128198A TW94128198A TWI268553B TW I268553 B TWI268553 B TW I268553B TW 094128198 A TW094128198 A TW 094128198A TW 94128198 A TW94128198 A TW 94128198A TW I268553 B TWI268553 B TW I268553B
Authority
TW
Taiwan
Prior art keywords
gate dielectric
modifying
dielectric stack
plasma
layer
Prior art date
Application number
TW094128198A
Other languages
English (en)
Chinese (zh)
Other versions
TW200618091A (en
Inventor
Hiroaki Niimi
Luigi Colombo
Koji Shimomura
Takuya Sugawara
Tatsuo Matsudo
Original Assignee
Tokyo Electron Ltd
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Electron Ltd, Texas Instruments Inc filed Critical Tokyo Electron Ltd
Publication of TW200618091A publication Critical patent/TW200618091A/zh
Application granted granted Critical
Publication of TWI268553B publication Critical patent/TWI268553B/zh

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/66—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials
    • H10P14/662—Laminate layers, e.g. stacks of alternating high-k metal oxides
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01332—Making the insulator
    • H10D64/01336—Making the insulator on single crystalline silicon, e.g. chemical oxidation using a liquid
    • H10D64/0134—Making the insulator on single crystalline silicon, e.g. chemical oxidation using a liquid with a treatment, e.g. annealing, after the formation of the insulator and before the formation of the conductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01332—Making the insulator
    • H10D64/01336—Making the insulator on single crystalline silicon, e.g. chemical oxidation using a liquid
    • H10D64/01344—Making the insulator on single crystalline silicon, e.g. chemical oxidation using a liquid in a nitrogen-containing ambient, e.g. N2O oxidation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/691—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator comprising metallic compounds, e.g. metal oxides or metal silicates 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6326—Deposition processes
    • H10P14/6328—Deposition from the gas or vapour phase
    • H10P14/6334—Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H10P14/6336—Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
    • H10P14/6921—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon
    • H10P14/6928—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material containing silicon and at least one metal element, e.g. metal silicate based insulators or metal silicon oxynitrides
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
    • H10P14/6938—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses the material containing at least one metal element, e.g. metal oxides, metal oxynitrides or metal oxycarbides
    • H10P14/6939—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses the material containing at least one metal element, e.g. metal oxides, metal oxynitrides or metal oxycarbides characterised by the metal
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P32/00—Diffusion of dopants within, into or out of wafers, substrates or parts of devices
    • H10P32/20—Diffusion for doping of insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/681—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered
    • H10D64/685—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered being perpendicular to the channel plane

Landscapes

  • Formation Of Insulating Films (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
TW094128198A 2004-08-18 2005-08-18 A method and system for modifying a gate dielectric stack containing a high-k layer using plasma processing TWI268553B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/920,990 US7163877B2 (en) 2004-08-18 2004-08-18 Method and system for modifying a gate dielectric stack containing a high-k layer using plasma processing

Publications (2)

Publication Number Publication Date
TW200618091A TW200618091A (en) 2006-06-01
TWI268553B true TWI268553B (en) 2006-12-11

Family

ID=35431477

Family Applications (1)

Application Number Title Priority Date Filing Date
TW094128198A TWI268553B (en) 2004-08-18 2005-08-18 A method and system for modifying a gate dielectric stack containing a high-k layer using plasma processing

Country Status (6)

Country Link
US (1) US7163877B2 (enExample)
JP (1) JP4950888B2 (enExample)
KR (1) KR101163264B1 (enExample)
CN (1) CN100568462C (enExample)
TW (1) TWI268553B (enExample)
WO (1) WO2006023373A1 (enExample)

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JPWO2007132884A1 (ja) * 2006-05-17 2009-09-24 株式会社日立国際電気 半導体装置の製造方法および基板処理装置
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US20100044804A1 (en) * 2008-08-25 2010-02-25 Taiwan Semiconductor Manufacturing Company, Ltd. Novel high-k metal gate structure and method of making
US8193586B2 (en) 2008-08-25 2012-06-05 Taiwan Semiconductor Manufacturing Company, Ltd. Sealing structure for high-K metal gate
US8252653B2 (en) * 2008-10-21 2012-08-28 Applied Materials, Inc. Method of forming a non-volatile memory having a silicon nitride charge trap layer
US8198671B2 (en) * 2009-04-22 2012-06-12 Applied Materials, Inc. Modification of charge trap silicon nitride with oxygen plasma
US8962454B2 (en) * 2010-11-04 2015-02-24 Tokyo Electron Limited Method of depositing dielectric films using microwave plasma
KR101893471B1 (ko) * 2011-02-15 2018-08-30 어플라이드 머티어리얼스, 인코포레이티드 멀티존 플라즈마 생성을 위한 방법 및 장치
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KR101246191B1 (ko) * 2011-10-13 2013-03-21 주식회사 윈텔 플라즈마 장치 및 기판 처리 장치
US8890264B2 (en) * 2012-09-26 2014-11-18 Intel Corporation Non-planar III-V field effect transistors with conformal metal gate electrode and nitrogen doping of gate dielectric interface
US9224644B2 (en) * 2012-12-26 2015-12-29 Intermolecular, Inc. Method to control depth profiles of dopants using a remote plasma source
US9343291B2 (en) * 2013-05-15 2016-05-17 Tokyo Electron Limited Method for forming an interfacial layer on a semiconductor using hydrogen plasma
US9331168B2 (en) 2014-01-17 2016-05-03 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and manufacuturing method of the same
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US20170084464A1 (en) * 2015-09-18 2017-03-23 Tokyo Electron Limited Germanium-containing semiconductor device and method of forming
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US11152214B2 (en) * 2016-04-20 2021-10-19 International Business Machines Corporation Structures and methods for equivalent oxide thickness scaling on silicon germanium channel or III-V channel of semiconductor device
TWI635539B (zh) * 2017-09-15 2018-09-11 Corremax International Co., Ltd. 高介電常數介電層、其製造方法及執行該方法之多功能設備
KR102384865B1 (ko) 2018-01-31 2022-04-08 삼성전자주식회사 반도체 소자 제조 방법
CN112133634A (zh) * 2018-05-25 2020-12-25 中国科学院微电子研究所 基于微波等离子体氧化的凹槽mosfet器件的制造方法
US11417517B2 (en) * 2019-05-03 2022-08-16 Applied Materials, Inc. Treatments to enhance material structures
US20210057215A1 (en) * 2019-05-03 2021-02-25 Applied Materials, Inc. Treatments to enhance material structures
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Also Published As

Publication number Publication date
CN101006566A (zh) 2007-07-25
KR20080009675A (ko) 2008-01-29
WO2006023373A1 (en) 2006-03-02
CN100568462C (zh) 2009-12-09
US20060040483A1 (en) 2006-02-23
JP2008510319A (ja) 2008-04-03
TW200618091A (en) 2006-06-01
KR101163264B1 (ko) 2012-07-05
US7163877B2 (en) 2007-01-16
JP4950888B2 (ja) 2012-06-13

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