JP4942020B2 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
JP4942020B2
JP4942020B2 JP2006133680A JP2006133680A JP4942020B2 JP 4942020 B2 JP4942020 B2 JP 4942020B2 JP 2006133680 A JP2006133680 A JP 2006133680A JP 2006133680 A JP2006133680 A JP 2006133680A JP 4942020 B2 JP4942020 B2 JP 4942020B2
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JP
Japan
Prior art keywords
semiconductor chip
module substrate
main surface
electrode pads
bonding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2006133680A
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English (en)
Japanese (ja)
Other versions
JP2007305848A5 (https=
JP2007305848A (ja
Inventor
宏 黒田
勝彦 橋詰
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Electronics Corp
Original Assignee
Renesas Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Electronics Corp filed Critical Renesas Electronics Corp
Priority to JP2006133680A priority Critical patent/JP4942020B2/ja
Priority to US11/734,973 priority patent/US7745941B2/en
Priority to CN2007101022794A priority patent/CN101071810B/zh
Publication of JP2007305848A publication Critical patent/JP2007305848A/ja
Publication of JP2007305848A5 publication Critical patent/JP2007305848A5/ja
Priority to US12/780,395 priority patent/US8138611B2/en
Application granted granted Critical
Publication of JP4942020B2 publication Critical patent/JP4942020B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H10W72/07321—Aligning
    • H10W72/07323—Active alignment, e.g. using optical alignment using marks or sensors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07541—Controlling the environment, e.g. atmosphere composition or temperature
    • H10W72/07554—Controlling the environment, e.g. atmosphere composition or temperature changes in dispositions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/547—Dispositions of multiple bond wires
    • H10W72/5473—Dispositions of multiple bond wires multiple bond wires connected to a common bond pad
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/932—Plan-view shape, i.e. in top view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/951—Materials of bond pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/291—Configurations of stacked chips characterised by containers, encapsulations, or other housings for the stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/732—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/752—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/753—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between laterally-adjacent chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Wire Bonding (AREA)
JP2006133680A 2006-05-12 2006-05-12 半導体装置 Expired - Fee Related JP4942020B2 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2006133680A JP4942020B2 (ja) 2006-05-12 2006-05-12 半導体装置
US11/734,973 US7745941B2 (en) 2006-05-12 2007-04-13 Semiconductor device having shifted stacked chips
CN2007101022794A CN101071810B (zh) 2006-05-12 2007-05-09 半导体器件
US12/780,395 US8138611B2 (en) 2006-05-12 2010-05-14 Semiconductor device having shifted stacked chips

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2006133680A JP4942020B2 (ja) 2006-05-12 2006-05-12 半導体装置

Publications (3)

Publication Number Publication Date
JP2007305848A JP2007305848A (ja) 2007-11-22
JP2007305848A5 JP2007305848A5 (https=) 2009-06-18
JP4942020B2 true JP4942020B2 (ja) 2012-05-30

Family

ID=38684349

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006133680A Expired - Fee Related JP4942020B2 (ja) 2006-05-12 2006-05-12 半導体装置

Country Status (3)

Country Link
US (2) US7745941B2 (https=)
JP (1) JP4942020B2 (https=)
CN (1) CN101071810B (https=)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9275940B2 (en) 2013-07-19 2016-03-01 Renesas Electronics Corporation Semiconductor device and manufacturing method thereof

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100798896B1 (ko) * 2007-06-07 2008-01-29 주식회사 실리콘웍스 반도체 칩의 패드 배치 구조
JP2010177456A (ja) * 2009-01-29 2010-08-12 Toshiba Corp 半導体デバイス
JP5645371B2 (ja) 2009-05-15 2014-12-24 ピーエスフォー ルクスコ エスエイアールエルＰＳ４ Ｌｕｘｃｏ Ｓ．ａ．ｒ．ｌ． 半導体装置
US11457531B2 (en) 2013-04-29 2022-09-27 Samsung Display Co., Ltd. Electronic component, electric device including the same, and bonding method thereof
KR102379591B1 (ko) * 2014-04-10 2022-03-30 삼성디스플레이 주식회사 전자부품, 이를 포함하는 전자기기 및 전자기기의 본딩 방법
KR102247916B1 (ko) * 2014-01-16 2021-05-04 삼성전자주식회사 계단식 적층 구조를 갖는 반도체 패키지
US10777478B2 (en) 2016-07-15 2020-09-15 Advanced Semiconductor Engineering, Inc. Semiconductor package device for power device
KR102571267B1 (ko) * 2018-09-19 2023-08-29 에스케이하이닉스 주식회사 부분 중첩 반도체 다이 스택 패키지
TWI686924B (zh) * 2018-10-18 2020-03-01 普誠科技股份有限公司 積體電路及其測試方法
CN112309875A (zh) * 2020-11-02 2021-02-02 南方电网科学研究院有限责任公司 一种芯片封装方法
US12136623B2 (en) * 2020-11-11 2024-11-05 Infineon Technologies Austria Ag Multi-device semiconductor chip with electrical access to devices at either side

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5323060A (en) * 1993-06-02 1994-06-21 Micron Semiconductor, Inc. Multichip module having a stacked chip arrangement
JP3487524B2 (ja) * 1994-12-20 2004-01-19 株式会社ルネサステクノロジ 半導体装置及びその製造方法
JP2002043503A (ja) * 2000-07-25 2002-02-08 Nec Kyushu Ltd 半導体装置
JP2002057270A (ja) * 2000-08-08 2002-02-22 Sharp Corp チップ積層型半導体装置
JP4449258B2 (ja) * 2001-06-15 2010-04-14 ソニー株式会社 電子回路装置およびその製造方法
US6680219B2 (en) * 2001-08-17 2004-01-20 Qualcomm Incorporated Method and apparatus for die stacking
US6731011B2 (en) * 2002-02-19 2004-05-04 Matrix Semiconductor, Inc. Memory module having interconnected and stacked integrated circuits
JP2003338519A (ja) * 2002-05-21 2003-11-28 Renesas Technology Corp 半導体装置及びその製造方法
JP4615189B2 (ja) * 2003-01-29 2011-01-19 シャープ株式会社 半導体装置およびインターポーザチップ
JP4417150B2 (ja) * 2004-03-23 2010-02-17 株式会社ルネサステクノロジ 半導体装置
US8324725B2 (en) * 2004-09-27 2012-12-04 Formfactor, Inc. Stacked die module

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9275940B2 (en) 2013-07-19 2016-03-01 Renesas Electronics Corporation Semiconductor device and manufacturing method thereof

Also Published As

Publication number Publication date
US20070262431A1 (en) 2007-11-15
US8138611B2 (en) 2012-03-20
CN101071810A (zh) 2007-11-14
US20100219537A1 (en) 2010-09-02
JP2007305848A (ja) 2007-11-22
US7745941B2 (en) 2010-06-29
CN101071810B (zh) 2010-12-22

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