CN100517690C - 三维封装 - Google Patents

三维封装 Download PDF

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CN100517690C
CN100517690C CNB2006100045188A CN200610004518A CN100517690C CN 100517690 C CN100517690 C CN 100517690C CN B2006100045188 A CNB2006100045188 A CN B2006100045188A CN 200610004518 A CN200610004518 A CN 200610004518A CN 100517690 C CN100517690 C CN 100517690C
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lead frame
electrically connected
integrated circuit
lead
salient point
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CN1835228A (zh
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萧喜铭
王飞莹
周安乐
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NXP USA Inc
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Freescale Semiconductor Inc
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Abstract

本发明涉及一种三维封装及其形成方法。其中的电子器件(60)包括：与第一引线框(64)电连接的第一集成电路(IC)管芯；和与第二引线框(68)电连接的第二IC管芯(66)。通过至少一个柱凸点(72)将第一引线框(64)与第二引线框(68)电连接，其中所述至少一个柱凸点有选择地形成在需要第一引线框(64)与第二引线框(68)之间电连接的地方。用模压化合物(74)包封第一和第二引线框(64)和(68)、第一和第二IC管芯(62)和(66)以及至少一个柱凸点(72)。

Description

三维封装
技术领域
本发明一般涉及半导体器件的封装，更具体地说，是涉及一种三维(3D)封装和形成这种3D封装的方法。
背景技术
按照摩尔定律(Moor’s Law)，集成电路(IC)上每平方英寸的晶体管数量大约每18个月就翻一番，从而使得用相同的实际栽培(real estate)量提供更大的功能性成为可能。然而，由于印刷电路板(PCB)的布线容量没有以相应的速率增大，因此系统级的互连密度不容乐观，从而限制了由于IC技术的改进而得到的功能性的增大。
最终，开发了3D封装，用来桥接IC与PCB之间的密度差。3D封装包括将两个或更多管芯(die)叠加在一个封装内，或者将完整封装叠加并连接起来。3D封装与现存封装相比，使得尺寸明显减小，这是因为此封装在每平方厘米的板空间和每立方厘米的应用空间堆积了更多的硅功能。根据这些或许多其它优点，3D封装正在夺取更大的IC封装市场份额。由此，期望有一种廉价的、形成具有改进特征的3D封装的方法。
发明内容
据此，本发明的一个目的是，提供一种具有改进特征的3D封装和制造这种封装的廉价方法。
根据本发明，提供了一种三维封装，包括：
与第一引线框电连接的第一集成电路管芯；
与第二引线框电连接的第二IC管芯，其中所述第一引线框叠加在所述第二引线框上；
至少一个将所述第一引线框和所述第二引线框电连接的柱凸点，其中所述至少一个柱凸点有选择地形成在需要所述第一引线框与所述第二引线框之间电连接的地方；
包封所述第一和第二引线框、所述第一和第二集成电路管芯以及所述柱凸点的模压化合物；以及
与所述三维封装的一个侧面上的至少一个端子电连接的无源电子器件，其中，所述无源电子器件将所述三维封装与第二三维封装电连接。
根据本发明，提供了一种3D封装，它们比现存的产品和工艺具有益处。举例来说，通过使柱凸点有选择地形成在需要两个相邻管芯的选择性部分之间电连接的地方，利用本发明能够使3D封装设计具有更大的多面性。利用本发明还可实现低制造成本，这是因为柱凸点形成在与引线框与管芯之间电连接相同的通路上，借此无需形成柱凸点的额外工艺步骤。此外，本发明通过在可叠加的封装集成电路的每一侧面上配置端子，使得成品的小型化容易并提高了产品的总产量。而且，由于本发明能够利用目前的半导体组装设备来实施，因此无需额外的基本投资。
附图说明
本发明优选实施例的以下详细描述在结合附图进行阅读时，将得到更好的理解。本发明借助于实例进行阐述，并且不受附图的限制，其中类似的附图标记表示类似的部件。
图1-4是按照本发明的一个实施例形成多个叠加管芯组件的方法的放大截面图；
图5是按照本发明一个实施例的引线框板边缘的放大透视图；
图6是按照本发明一个实施例的3D可叠加封装的放大截面图；
图7是图6的3D可叠加封装和按照本发明一个实施例的无源电子器件的透视图；
图8是两个并排放置的3D可叠加封装和按照本发明进一步实施例的无源电子器件的透视图；
图9是按照本发明另一个实施例、与引线框电连接的IC管芯的放大截面图；
图10是按照本发明另一个实施例的3D可叠加封装的放大截面图；以及
图11是图10的3D可叠加封装和按照本发明一个实施例的无源电子器件的透视图。
具体实施方式
以下结合附图阐明的详细描述意在对作为本发明目前优选实施例的描述，并没有代表可实践本发明的唯一形式的意思。应该理解，利用打算包含在本发明的精髓和范围内的不同实施例，可获得相同或等同的功能。
为了实现上述及其它目的和优点，本发明提供了三维封装器件，该器件包括与第一引线框电连接的第一集成电路(IC)管芯，和与第二引线框电连接的第二IC管芯。第一引线框经由至少一个柱凸点(stud bump)叠加到第二引线框上并与之电连接。所述至少一个柱凸点有选择地形成在需要第一引线框与第二引线框之间电连接的地方。第一和第二引线框、第一和第二IC管芯以及所述至少一个柱凸点被模压化合物(mold compound)所包封，从而形成可叠加的3D封装器件。
本发明还提供了一种形成3D封装器件的方法。该方法包括使第一IC管芯与第一引线框、第二IC管芯与第二引线框电连接的步骤。至少一个柱凸点有选择地形成在第一引线框上，在该处需要第一引线框与第二引线框之间电连接。第一引线框经由所述至少一个柱凸点与第二引线框电连接。然后，包封第一和第二引线框、第一和第二IC管芯以及所述至少一个柱凸点，从而形成可叠加的3D封装器件。
本发明进一步提供了一种形成多个3D封装的方法，该方法包括使第一多个半导体IC管芯与第一引线框板的第一引线框的相应管芯接收区域电连接，以及使第二多个半导体IC管芯与第二引线框板的第二引线框的相应管芯接收区域电连接。多个柱凸点有选择地形成在第一引线框板的第一引线框上，每个柱凸点有选择地形成在需要相应两个第一引线框与第二引线框之间电连接的地方。第二引线框板叠加在第一引线框板上。第一和第二引线框板可以与定位栓对准。第一和第二多个引线框的彼此相应的两个之间借助于柱凸点连接起来。实施模制操作，以包封第一和第二多个IC管芯、电连接和柱凸点。其后，实施单切操作，以便使相邻叠加的第一和第二IC管芯分开，借此形成多个叠加管芯组件。
图1-4图示出按照本发明的一个实施例形成多个叠加管芯组件10的方法。
图1表示出附着到第一引线框板18的第一引线框16的相应管芯接收区域14上的第一多个半导体集成电路(IC)管芯12，图2表示出附着到第二引线框板26的第二引线框24的相应管芯接收区域22上的第二多个半导体集成电路(IC)管芯20。
IC管芯12和20可以是处理器，例如数字信号处理器(DSP)、特殊功能电路(诸如存储器地址发生器)或执行任何其它类型功能的电路。IC管芯12和20不限于特定技术例如CMOS，或派生于任何特定的晶片技术。而且，本发明能够供给多种管芯尺寸，这正如本领域技术人员所理解的。一般的实例是，具有约10mm×10mm尺寸的微处理器或存储芯片。虽然图1和2每个仅表示出两个(2)管芯，但是应该理解，根据第一和第二引线框板18和26的尺寸、IC管芯12和20的尺寸以及所产生的叠加管芯组件10的所需功能性，更多或更少的管芯可以附着到第一和第二引线框板18和26上。在此具体实例中，IC管芯12和20经由多个接合引线28电连接到引线框16和24的引线上。不过，应该理解，本发明不限于引线接合型连接。在其它实施例中，IC管芯12和20诸如可以经由倒装片凸点(参见图9和10)电连接到各自的引线框16和24的引线上。
如图1和2所示，第一和第二引线框板18和26的每一个都包括各自的带30和32，这些带粘附到第一和第二多个引线框16和24的相应第一侧面34和36上。在此具体实例中，第一和第二多个引线框16和24是蚀刻的铜引线框，而带30和32是管芯掩蔽带。引线框板18和26可包括引线框矩阵，例如3x 6矩阵，这正如本领域内所公知的并且一般在商业上可获得。然而，应该理解，本发明不限于特定类型的引线框或带，或制造引线框的材料。例如，第一和第二多个引线框16和24可以通过蚀刻或冲压来形成。
第一和第二引线框16和24的厚度涉及第一和第二IC管芯12和20的相应厚度和最终形成的封装的厚度。具体地说，在图1-4所示的实施例中，第一和第二引线框16和24的高度略大于相应IC管芯12和20的厚度加上接合引线28制成的环高度。如果第一和第二多个IC管芯12和20经由倒装片凸点(参见图9中的倒装片凸点104，以下描述)与相应的第一和第二多个引线框16和24耦合，那么第一和第二引线框16和24的厚度应该至少等于相应第一和第二IC管芯12和20的厚度+倒装片凸点的高度+倒装片凸点所在的第一和第二引线框16和24基底的高度。虽然图9和10表示出在IC管芯顶部之外延伸的引线框，但是引线框与IC管芯的顶部共面。虽然图1-4所示的第一和第二引线框16和24具有基本相同的尺寸，但是应该理解，第一和第二多个引线框16和24根据相应第一和第二多个IC管芯12和20的厚度，可以具有不同的尺寸。
现在参照图1，多个柱凸点38在第一引线框板18(如图所示)的第一引线框16上形成。柱凸点38是用导电材料例如金形成的，并且可以用引线接合机来形成。每个柱凸点38有选择地形成在需要第一引线框16与第二引线框24之间电连接的地方。通过有选择地形成柱凸点38，能够有选择地限定部分第一和第二多个IC管芯12和20部分之间的电连接，借此为叠加管芯组件10提供较大的多面性。据此，在没有柱凸点38的情况下，第一IC管芯12与第二IC管芯20的相应部分之间没有电连接。例如，中心引线框16仅具有一个在其上的柱凸点38。
在一个实施例中，在与第一IC管芯12和第一引线框16之间的电连接相同的通路(pass)中，利用线接合器形成柱凸点38。通过这样做，形成柱凸点的额外工艺步骤得以消除，借此降低最终产品的制造成本。
图3表示出叠加在第一引线框板18上的第二引线框板26。第二引线框板26是在叠加之前倒装的，从而第二多个IC管芯20的顶部(接合引线28从此处延伸)正面对第一多个IC管芯12的顶部。第一和第二引线框板18和26与一个或多个定位栓对准。如图所示，第一和第二多个引线框18和24彼此相应的二者之间借助于柱凸点38相连。虽然引线框板18和26在此具体实施例中是与彼此面对的相应第一和第二多个IC管芯12和20叠加在一起的，但是应该理解，本发明不限于这样的设置。在其它实施例中，引线框板的叠加是为了使所有IC管芯面向同一方向(参见图10)，或两个方向的组合。
现在参照图4，用密封剂材料40包封第一和第二多个IC管芯12和20、电连接和柱凸点38。密封剂材料40可包括公知的商业上可获得的模压材料例如塑料或环氧树脂。
实施模压操作例如注模工艺，以便包封第一和第二多个IC管芯12和20、电连接和柱凸点38。适合这种模压操作性能的引线框板50在图5中示出。图5是按照本发明一个实施例的引线框板50的边缘52的放大透视图。如图所示，引线框板50的边缘52包括半蚀刻部分54。引线框板50的半蚀刻部分54形成叠加的引线框板18与26之间的密封剂材料40的注射和流动通道。蚀刻引线框的现存技术可用来制造具有半蚀刻边缘52的引线框板50。
再参照图4，每个柱凸点38由于模制压力而变形，从而在模制操作过程中在相应的第一和第二引线框16和24之间形成接头。如图所示，将带30和32从第一和第二多个引线框16和24上除去，以便暴露第一和第二多个引线框16和24的相应第一侧面34和36上的端子44和46。在第一和第二多个IC管芯12和20经由接合引线28电连接到第一和第二多个引线框16和24上的这个具体实例中，第一和第二引线框16和24的脱开(detaping)也暴露出每个第一和第二多个IC管芯12和20的表面。
相邻两个叠加的第一和第二IC管芯12和20经由单切操作(例如形成多个叠加模组件10的锯划方法)沿垂直线A-A、B-B和C-C分开。单切步骤优选地在脱开之前实施。然而，单切步骤也可能在将带30，32从引线框板18和26上除去之后实施。
现在参照图6，该图表示出按照图1-4所示方法形成的3D可叠加封装集成电路60的放大截面图。封装集成电路60包括与第一引线框64电连接的第一IC管芯62，和与第二引线框68电连接的第二IC管芯66。第一和第二IC管芯62和66经由多个接合引线70与相应的第一和第二引线框64和68电连接，而第一引线框64经由至少一个柱凸点72与第二引线框68电连接，所述至少一个柱凸点有选择地形成在需要第一引线框64与第二引线框68之间电连接的地方。第一和第二引线框64和68、第一和第二IC管芯62和66以及柱凸点72被模压化合物74所包封，从而形成可叠加的封装集成电路。在这个具体实例中，可叠加的封装集成电路60具有约0.5毫米(mm)的总厚度或高度。然而，应该理解，本发明不受可叠加的封装集成电路的厚度的限制。而是，可叠加的封装集成电路的厚度取决于引线框的厚度和被叠加的IC数目。在图示的实施例中，IC管芯62和66每个具有约4密尔的厚度，第一和第二引线框64和68每个具有约8密尔的厚度，用于引线框内连接的柱凸点72具有约5-6密尔的厚度，这导致总的封装厚度为约21-22密尔。用于注模的模腔容许约20密尔的厚度，于是当模具闭合时，柱凸点72由于模制压力而变形，从而在第一和第二引线框16和68之间形成接头，并且最终的封装集成电路60具有约20密尔或0.5mm的总厚度。用来将集成电路62和66保持在引线框64和68的管芯接收区的模制掩蔽带避免模制操作过程中的树脂溢流。
现在参照图7，该图表示出无源电子器件78例如电容器或电阻器与图6的可叠加封装集成电路60的电连接。如图7所示，可叠加的封装集成电路60是Quad Flat无引线型封装，在六(6)侧可叠加的封装集成电路60的每一侧上配有多个端子80。多个端子80在可叠加的封装集成电路60的每一排上的配置，容易使成品小型化，因为它允许更有效地使用板空间和应用空间。此外，由于该特性在叠加之前进行老化及电功能测试，因此在叠加之前鉴定出并弃掉有故障的可叠加封装集成电路，借此提高成品的总产量。
本领域的技术人员应该理解，本发明不局限于图7所示的具体实例。在其它实施例中，可叠加的封装集成电路60经由可叠加的封装集成电路60的任一侧上的一个或多个端子80，可以与一个或多个电子元件例如无源器件、传感器模块、半导体封装、IC管芯、这些元件组成的电路或组合电连接。例如，可叠加的封装集成电路60的顶表面上的端子80通过两个可叠加的封装集成电路上的相应端子之间形成的外部焊接头连接，可以与第二可叠加的封装集成电路电连接，而可叠加的封装集成电路60的底表面安装到PCB上。
本发明的另一个示范性实施例在图8中示出。图8表示出与带有无源电子器件84的第二可叠加的封装集成电路82电连接的图6的可叠加封装集成电路60。在这个具体实施例中，可叠加的封装集成电路60和82通过可叠加的封装集成电路60和82顶表面上的相应端子80和86进行桥接。
现在参照图9，该图表示出有第一IC 102与其电连接的第一引线框100。第一IC 102经由多个倒装片凸点104与第一引线框100电连接。带106例如模制掩蔽带捆扎到第一引线框100的第一侧面108上。在第一引线框100上形成多个柱凸点110，用于使第一引线框100与叠加在其上的另一个引线框相连。在倒装片连接的一个示范性实施例中，如图9所示，在此实施例中，第一IC具有约4密尔的厚度，第一引线框100具有约8密尔的厚度，用于引线框内连接的柱凸点110具有约5-6密尔的厚度。在模制过程中，柱凸点110由于模具的闭合而发生变形。如果不使用模制掩蔽带，则由于无需将集成电路102保持在引线框100的管芯接收区内，因此可发生树脂溢出，如果柱凸点太小的话。
现在参照图10，图9的第一引线框100在其上叠加了多个连续的引线框112分别与相应的IC管芯114电连接，每一个引线框100和112通过多个柱凸点110和116中的相应一个与相邻引线框电连接。如图所示，柱凸点110和116中的每一个有选择地形成在相邻引线框之间需要电连接的地方。引线框100和112、IC管芯102和14以及柱凸点110和116用密封剂材料例如塑料或环氧树脂包封，从而形成可叠加的封装集成电路120。注意，引线框100和112不以类似于图6中的引线框64和68的面对面关系进行叠加。由此，图9所示的结构使得奇数个引线框彼此叠加更容易。
现在参照图11，该图表示出图10的彼此叠加的多个可叠加封装集成电路120和无源电子器件122的透视图。在该图中，五(5)个IC叠加在一起。可叠加的封装集成电路120在其六(6)个侧面的每一个上配有多个端子124。无源电子器件122经由端子124与可叠加的封装集成电路120之一电连接。在这个实施例中，无源器件122与封装器件120的顶部相连。然而，正如所理解的，无源器件122可能利用其侧面上的端子连接到封装120的任一侧面上。在其它实施例中，可叠加的封装集成电路120经由可叠加封装集成电路120任一侧面上的任一端子124，可以与一个或多个其它电子元件例如传感器模块、半导体封装或电路电连接。
正如从以上论述明显易见的，本发明提供了一种3D封装和形成这种3D封装的方法，它们比现存的产品和工艺具有益处。举例来说，通过使柱凸点有选择地形成在需要两个相邻管芯的选择性部分之间电连接的地方，利用本发明能够使3D封装设计具有更大的多面性。利用本发明还可实现低制造成本，这是因为柱凸点形成在与引线框与管芯之间电连接相同的通路上，借此无需形成柱凸点的额外工艺步骤。此外，本发明通过在可叠加的封装集成电路的每一侧面上配置端子，使得成品的小型化容易并提高了产品的总产量。而且，由于本发明能够利用目前的半导体组装设备来实施，因此无需额外的基本投资。
由此，显而易见的是，按照本发明，已经提供了一种完全满足以上提到的优点的可叠加封装和这种可叠加封装的形成方法。虽然已经参照本发明的具体实施例对本发明进行了描述和图示，但是并无意将本发明限定于这些图示的实施例。本领域的技术人员应该认识到，在不脱离本发明精髓的前提下能够做出修改和变型。例如，本发明允许叠加任何数目的管芯和封装。正如更早提出的，本发明不限于管芯面对方向、所用的引线框类型或引线框和成品的尺寸。器件的结构也不限于倒装片和线接合应用。应该理解，本发明可以通过在同一电子器件中混合使用倒装片和线接合技术，可利用叠加形式的多功能硅晶片来实施。而且，本发明不限于本文所述或图示的那些类型的半导体管芯。因此，本发明意在包含所有这样的变型和修改，正如落在所附权利要求书的范围内一样。

Claims (7)

1、一种三维封装，包括：
与第一引线框电连接的第一集成电路管芯；
与第二引线框电连接的第二集成电路管芯，其中所述第一引线框叠加在所述第二引线框上；
至少一个将所述第一引线框和所述第二引线框电连接的柱凸点，其中所述至少一个柱凸点有选择地形成在需要所述第一引线框与所述第二引线框之间电连接的地方；
包封所述第一和第二引线框、所述第一和第二集成电路管芯以及所述柱凸点的模压化合物；以及
与所述三维封装的一个侧面上的至少一个端子电连接的无源电子器件，其中，所述无源电子器件将所述三维封装与第二三维封装电连接。
2、根据权利要求1所述的三维封装，其特征在于，所述三维封装是四方扁平无引线型封装。
3、根据权利要求1所述的三维封装，其特征在于，在所三维述封装的每个侧面上还包括多个端子。
4、根据权利要求1所述的三维封装，其特征在于，所述无源电子器件是电容器和电阻器之一。
5、根据权利要求1所述的三维封装，其特征在于，还包括与第三引线框电连接的第三集成电路管芯，其中所述第三引线框叠加在所述第二引线框上并利用多个柱凸点与其电连接，所述模压化合物包封所述第一、第二和第三引线框、所述第一、第二和第三集成电路管芯以及所述柱凸点。
6、根据权利要求1所述的三维封装，其特征在于，所述第一集成电路管芯经引线接合与所述第一引线框电连接。
7、根据权利要求1所述的三维封装，其特征在于，所述第一集成电路管芯利用多个第二柱凸点作为倒装片与所述第一引线框电连接。
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US7262494B2 (en) 2007-08-28
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TWI287864B (en) 2007-10-01

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