CN101071810A - 半导体器件 - Google Patents

半导体器件 Download PDF

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Publication number
CN101071810A
CN101071810A CNA2007101022794A CN200710102279A CN101071810A CN 101071810 A CN101071810 A CN 101071810A CN A2007101022794 A CNA2007101022794 A CN A2007101022794A CN 200710102279 A CN200710102279 A CN 200710102279A CN 101071810 A CN101071810 A CN 101071810A
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China
Prior art keywords
semiconductor chip
module substrate
electrode pad
lead
bonding
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Granted
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CNA2007101022794A
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CN101071810B (zh
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黑田宏
桥诘胜彦
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Renesas Electronics Corp
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Renesas Technology Corp
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  • Engineering & Computer Science (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)

Abstract

关于可以在功能上直接连接的电极焊盘之间的互连，提供了可以有助于模块衬底小型化的半导体器件。进行了叠置的第一半导体芯片和第二半导体芯片以与模块衬底之间中心位置相互左右偏离的方式安装在模块衬底上。在从偏离的半导体芯片的边缘到模块衬底的边缘的距离较短的一侧上，第一半导体芯片上的电极焊盘和相互对应的第二半导体芯片上的电极焊盘利用导线直接连接。在从偏离的半导体芯片的边缘到模块衬底的边缘的距离较长的一侧上，第一半导体芯片上的电极焊盘和第二半导体芯片上的电极焊盘利用导线与模块衬底上对应的键合引线相结合。

Description

半导体器件
相关申请的交叉引用
本申请要求于2006年5月12日提交的日本专利申请No.2006-133680的优先权，据此将其内容通过参考引入本申请。
技术领域
本发明涉及叠置结构的系统级封装(SIP)的半导体器件，其中将两个半导体芯片堆积并容纳在一个封装中。
背景技术
在进行两个半导体芯片叠置的SIP中，将诸如球栅阵列(BGA)的模块端子布置在模块衬底的背表面中。在模块衬底的表面上，形成与模块端子结合的键合引线。利用导线，将所叠置的两个半导体芯片的对应电极焊盘连接到键合引线。当沿着两个半导体芯片的同一侧布置多个电极焊盘时，沿着模块衬底的一侧，以前后两行布置与它们连接的键合引线。例如，利用导线将前一行的键合引线连接到朝下布置的半导体芯片的电极焊盘，并且利用导线将后一行的键合引线连接到朝上布置的半导体芯片的电极焊盘。对于这样的连接配置，由于当把上半导体芯片的电极焊盘直接连接到对应的键合引线并且连接导线变长时，存在导线与半导体芯片和其它导线接触的问题，所以在专利文献1中示出了下列结构作为从上半导体芯片的电极焊盘到对应的键合引线的连接，即，中继端子形成在下半导体芯片中，导线从上半导体芯片的电极焊盘连接到中继端子，以及导线从中继端子连接到对应的键合引线。特别是在专利文献1中，由于朝上叠置的半导体芯片的尺寸受其中将中继端子布置到所叠置的下半导体芯片两侧的这样结构限制，所以提出一种结构，其中去掉一个中继端子，使结构偏离到失去中继端子的那一侧，并且在其上叠置另一半导体芯片。通过使上半导体芯片靠近于下半导体芯片的边界部分，并且使其偏离，可以使将上半导体芯片的电极焊盘连接到模块衬底的键合引线的导线变短到可以在靠近的那侧处直接连接的程度。作为结果，推测到可以从朝下叠置的半导体芯片一侧除去中继端子，并且可实现朝下叠置的半导体芯片的小型化。
[专利文献1]日本未审专利公开No.2002-43503
发明内容
关于在功能上可以直接连接的电极焊盘，如形成存储控制器的地址输出端子的电极焊盘以及形成存储器的地址输入端子的电极焊盘，可采用这样的结构：每个电极焊盘连接到键合引线，并且对应的键合引线与模块衬底中的布线结合。即使是在功能上可以直接连接的电极焊盘，也要应对其中它们的排列没有相互聚集的情况。
然而，当键合引线的数目增加时，例如进行两级半导体芯片的叠置时，与第一级半导体芯片对应的键合引线行以及与所叠置的第二级半导体芯片对应的键合引线行将分别在半导体芯片的左和右(或周围)布置成两行，并且变得难以使模块衬底小型化。专利文献1的技术倾向于通过使上半导体芯片与所叠置的下半导体芯片偏离并进行布置，而使下半导体芯片的尺寸较小。其中没有关于在信号输入输出功能上可以直接连接的电极焊盘之间的互连方面使模块衬底小型化的暗示。
当对第一级半导体芯片进行倒装芯片连接，使得前表面(电极焊盘形成表面)可以面对模块衬底的前表面(键合引线形成表面)时，由于与第一级半导体芯片的电极焊盘对应的多个键合引线不会布置在半导体芯片的周围下方，而布置在半导体芯片的背表面下方，所以模块衬底的小型化是可能的。然而，当应用倒装芯片连接时，与导线键合方法相比，制造成本将变高。
于是，本发明人研究了当在功能上可以直接连接的电极焊盘的排列在所叠置的半导体芯片之间聚集到一定程度时，直接连接这种电极焊盘的情况。通过直接连接，因为可以减少模块衬底上的键合引线的数目，并且可以使得在模块衬底内对应的键合引线之间连接的布线变得不必要，所以可有助于模块衬底的简化。然而，即使这可以减少键合引线的数目，但如果其空区域分散在模块衬底上，则也无法有助于模块衬底的小型化。
本发明的目的在于提供关于在功能上可以直接连接的电极焊盘之间的互连，可以有助于模块衬底的小型化的半导体器件。
本发明的目的在于提供可以降低半导体器件的制造成本的技术。
从这里的描述和附图，本发明的上述以及其它目的和新颖特征将变得显而易见。
下面将简要地概述在本申请公开的发明中的典型发明。
[1]关于本发明的半导体器件(4)具有模块衬底(3)、第一半导体芯片(1)和第二半导体芯片(2)。该模块衬底包括沿第一侧(301)布置的多个第一键合引线(303)、沿第一侧布置的比第一键合引线更靠近第一侧的多个第二键合引线(302)以及沿与第一侧相对的第二侧(306)布置的多个第三键合引线(307)。第一半导体芯片包括集成的第一电路、沿第三侧(100)布置并且耦合到第一电路的多个第一电极焊盘(101)和沿与第三侧相对的第四侧(104)布置并且耦合到第一电路的多个第二电极焊盘(105)，并且该第一半导体芯片安装在模块衬底上方。第二半导体芯片包括集成的第二电路、沿第五侧(200)布置并且耦合到第二电路的多个第三电极焊盘(201)和沿与第五侧相对的第六侧(204)布置并且耦合到第二电路的多个第四电极焊盘(205)，并且该第二半导体芯片安装在第一半导体芯片上方。第一键合引线和对应的第一电极焊盘通过第一导线(502)分别电连接。第二键合引线和对应的第三电极焊盘通过第二导线(501)分别电连接。第三键合引线和对应的第二电极焊盘通过第三导线(507)分别电连接。第二电极焊盘和对应的第四电极焊盘通过第四导线(500)分别电连接。第三侧和第五侧靠近第一侧而布置，第四侧和第六侧靠近第二侧而布置，第一侧和第三侧的间隙大于第二侧和第四侧的间隙。
根据上述方式，通过第一半导体芯片和第二半导体芯片同一侧的边界部分，汇集可利用第四导线直接连接的第二电极焊盘和第四电极焊盘。从沿着模块衬底的第二侧(306)布置的多个键合引线中，可以消除用于连接第二电极焊盘和第四电极焊盘的键合引线。因此，减少集中在该部分上的键合引线的数目成为可能。由直接连接产生的空区域集中到模块衬底的第二侧而没有分散。作为结果，沿第二侧布置的键合引线变得可以从多行排成为一排。由于第一和第二半导体芯片偏靠于第二侧而布置，所以在模块衬底的第一侧产生大的空间余地，并且变得易于布置大量的键合引线。这会有助于实现模块衬底的制造便利性和模块衬底的小型化。暂且来说，如果第一和第二半导体芯片不偏离到模块衬底的第二侧，则在模块衬底的第一侧上，就必需以相对高的密度来布置大量的键合引线，并且必需形成模块中的布线。因此模块衬底的制造变得困难并且限制了小型化。
由于第一和第二半导体芯片的每一个都经由多个键合导线而与形成在模块衬底上的多个键合引线电连接，所以这可以降低半导体器件的制造成本。
作为本发明的一个具体形式，使第三侧和第五侧的间隙与第四侧和第六侧的间隙相等。关于第一半导体芯片和第二半导体芯片的叠置，如常规技术那样，可以调整芯片中心并且可以容易地进行叠置。
作为本发明的另一个具体形式，对于共享第四导线的第二电极焊盘和第四电极焊盘，一方是输出端子，另一方是输入端子。这被设定为不同半导体芯片之间直接连接端子的典型的相互关系。
作为本发明的另一个具体形式，第三键合引线的数目少于第一键合引线的数目。模块衬底的第一侧上的空间余量可以进一步扩大。
[2]关于本发明的半导体器件(4)具有模块衬底(3)、第一半导体芯片(1)和第二半导体芯片(2)，其中第一半导体芯片安装在模块衬底上方，与该模块衬底之间中心位置相互左右偏离，并且其中集成了第一电路，而第二半导体芯片安装在第一半导体芯片上方并且其中集成了第二电路。在其中从偏离的第一半导体芯片的边缘到模块衬底的边缘的距离较短的一侧处，利用导线(500)直接连接在第一半导体芯片上方的电极焊盘(105)和相互对应的在第二半导体芯片上方的电极焊盘(205)。在其中从偏离的第一半导体芯片的边缘到模块衬底的边缘的距离较长的一侧处，利用导线(502、501)将在第一半导体芯片上方的电极焊盘(101)和在第二半导体芯片上方的电极焊盘(201)连接到模块衬底上方对应的键合引线(303、302)。
根据上述方式，在模块衬底上，由于半导体芯片偏离到其中布置了利用导线所直接连接的电极焊盘的那侧，所以在模块衬底上半导体芯片的相对侧上给出了大的空间余地。变得易于布置许多的键合引线并且可以有助于实现模块衬底的制造便利性和模块衬底的小型化。
作为本发明的一个具体形式，在其中从偏离的第一半导体芯片的边缘到模块衬底的边缘的距离较短的一侧处，利用导线结合在第一半导体芯片上的电极焊盘和相互对应的在模块衬底上的键合引线。在其中从偏离的第一半导体芯片的边缘到模块衬底的边缘的距离较短的一侧处，不需要指定为与第一半导体芯片的电极焊盘和第二半导体芯片的电极焊盘都直接连接，从这个意义上来说，灵活性增加。
以下将简要描述通过本申请公开的发明的最典型方面中的一些方面所实现的优点。
也就是，关于在功能上可以直接连接的电极焊盘之间的互连，可以使半导体器件的模块衬底小型化。
可以降低半导体器件的制造成本。
附图说明
图1是示出了关于本发明的半导体器件的示例的平面图；
图2是示出了关于第一比较示例的半导体器件的平面图，其中在不将半导体芯片与模块衬底偏离的情况下进行了叠置；
图3是示出了关于第二比较示例的半导体器件的平面图，其中将所叠置的半导体器件之间在功能上可以直接连接的电极焊盘各自地连接到模块衬底的键合引线，并且利用模块衬底中的布线相互连接这些对应的键合引线；
图4是示出了本发明的半导体器件的制造工艺的流程图；
图5是本发明的模块衬底的示意平面图；
图6是沿图5的A-A’线所取的示意横截面图；
图7是将第一半导体芯片安装在模块衬底上的示意平面图；
图8是沿图7的A-A’线所取的示意横截面图；
图9是将第二半导体芯片安装在第一半导体芯片上的示意平面图；
图10是沿图9的A-A’线所取的示意横截面图；
图11是第一和第二半导体芯片的每一个与模块衬底进行导线键合的示意平面图；
图12是沿图11的A-A’线所取的示意横截面图；
图13是沿图11的A-A’线所取的示意横截面图，其中在模块衬底上形成了密封体；以及
图14是其中在模块衬底的背表面处布置了多个球电极的沿图11的A-A’线所取的示意横截面图。
具体实施方式
在图1中以平面图示出了关于本发明的半导体器件的示例。该图中所示的半导体器件4具有SIP结构，其是通过将第一半导体芯片1和第二半导体芯片2叠置到模块衬底(布线衬底)3上而形成的。
第二半导体芯片2是向CCD照相机输出驱动电压的驱动器，而第一半导体芯片1是生成控制CCD照相机操作的定时控制信号的定时控制器。驱动器输入定时控制器所生成的定时控制信号的一部分，并且向CCD照相机供给驱动信号。
叠置在矩形的第一半导体芯片上的矩形的第二半导体芯片2具有沿侧(第五侧)200布置的多个电极焊盘(第三电极焊盘)201，具有沿侧202布置的多个电极焊盘203，并具有沿侧(第六侧)204布置的多个电极焊盘(第四电极焊盘)205。电极焊盘205与第一半导体芯片1通过接口连接，并被指定例如输入定时控制信号或输出应答信号的功能。尽管没有具体示出，但第二半导体芯片2设置有电压生成电路、输出电路等作为实现该功能的内部电路(第二电路)。电极焊盘201、203和205经由布线层而与形成在半导体芯片2内部的内部电路的预定节点相结合。
矩形的第一半导体芯片1具有沿侧(第三侧)100布置的多个电极焊盘(第一电极焊盘)101，具有沿侧102布置的多个电极焊盘103，具有沿侧(第四侧)104布置的多个电极焊盘(第二电极焊盘)105、106，并具有沿侧107的多个电极焊盘108。电极焊盘105通过键合导线(第四导线)500而与第二半导体芯片2的对应电极焊盘205相结合。尽管没有具体示出，但第一半导体芯片1设置有用于定时控制的序列发生器或程序控制电路、外围电路等作为用于实现该功能的内部电路(第一电路)。电极焊盘101、103、105、106和108经由布线层而与形成在半导体芯片2内部的内部电路的预定节点相结合。尽管没有具体限制，但第一半导体芯片具有模拟信号的输入/输出接口电路(例如，模拟-数字转换电路)。由沿侧107的电极焊盘108汇集连接到所述模拟I/O接口电路的电极焊盘，以便尽可能地避免与数字信号混合。
模块衬底3通过例如具有布线层的由玻璃环氧树脂制成的矩形布线衬底来形成。在背表面中，以阵列形式布置多个球电极。从沿侧(第一侧)301的外侧在前表面中形成两行的多个键合引线(第二键合引线)302和多个键合引线(第一键合引线)303。形成一行沿侧304的多个键合引线305、一行沿侧(第二侧)306的多个键合引线(第三键合引线)307以及一行沿侧308的多个键合引线309。键合引线302通过键合导线(第二导线)501而与第二半导体芯片2的电极焊盘201相结合。键合引线303通过键合导线(第一导线)502而与第一半导体芯片1的电极焊盘101相结合。键合引线305通过键合导线505而与第二半导体芯片2的对应电极焊盘203相结合，并通过键合导线506而与第一半导体芯片1的对应电极焊盘103相结合。键合引线307通过键合导线(第三导线)507而与第一半导体芯片1的电极焊盘106相结合。键合引线309通过键合导线508而与第一半导体芯片1的电极焊盘108相结合。尽管没有具体示出，但每个键合引线302、305、307和309都经由通孔或布线连接到对应的球电极。在模块衬底3的前表面上通过树脂密封并保护第一半导体芯片1、第二半导体芯片2以及键合导线500、501、502、505、506、507和508。
CL1是模块衬底3的中心线，CL2是半导体芯片1和2的中心线。如从图中可见，半导体芯片1和2调整中心线并进行叠置。进行了叠置的半导体芯片1和2的叠层向左侧偏离于(偏轴于)模块衬底3的中心线CL1。偏离量为EQ。由于需要相邻导线在导线键合中不接触，所以必需在相邻键合引线之间确保一个预定的最小间距。因此，通过将所叠置的半导体芯片1和2向左侧偏离于模块衬底3的中心线CL1并进行叠置，从而对布置间隔受限的模块衬底3上必需以两行布置键合引线302、303的区域产生了间隔余量。而在相对侧上应恰好布置一行键合引线307的区域中不会生成无用的空区域，结果可以有助于实现模块衬底3的小型化。如图2所示的第一比较示例，当调整模块衬底3的中心线CL1和半导体芯片1和2的中心线CL2而将它们叠置时，对于模块衬底3上半导体芯片1的左右区域AR1和AR2，其面积将变得相同。这基本上变得不可能通过向区域AR1布置两行键合引线而形成模块衬底，并且必需至少通过宽度W4(W1＜W4)形成模块衬底。在实践中由于成本或标准化的关系，难以采用任选尺寸的模块衬底。当在标准化模块衬底尺寸中没有W4时，必需采用比其大的尺寸W5的模块衬底尺寸，并且也会产生面积和成本上的大的浪费。当使得第一半导体芯片1的宽度尺寸W2＝3.68mm并且使得第二半导体芯片2的宽度尺寸W3＝2.4mm时，关于图1的半导体器件4的尺寸，通过使得偏离量EQ＝0.32mm，可采用宽度尺寸W1＝6mm的模块衬底3。另一方面，在图2的比较示例的情况中，则需要采用例如宽度尺寸W5＝8mm的模块衬底。
在图1的示例中，对于第一半导体芯片1的电极焊盘105和第二半导体芯片2的电极焊盘205而言，一方是输出端子，另一方是输入端子，并且它们是在功能上可以直接连接的端子。在图1中，其设置为这样的配置：通过将每个半导体芯片1和2的那些电极焊盘105、205汇集，使得它们可以位于作为共有的同一侧(在本发明中，例如为模块衬底的第二侧上)，从而可以利用导线500进行直接连接。在不考虑将第一半导体芯片1的电极焊盘105与第二半导体芯片2的电极焊盘205直接连接时，如图3的第二比较示例所示，必需利用导线将第一半导体芯片1的电极焊盘105和第二半导体芯片2的电极焊盘205分别与对应的键合引线311、310各自相结合。模块中通过相应件连接键合引线310和311的布线必需形成在模块衬底中。在图3的情况中，模块衬底3A中的布线不仅必需变得复杂，而且其必需对模块衬底3A的左右两侧各布置两行键合引线。因此，如图2的比较示例那样必需采用如W5的大尺寸的模块衬底。如从图2和图3的比较示例可见，在图2的结构中仅通过考虑直接连接电极焊盘105和205(该电极焊盘105和205在功能上可利用导线500在不同半导体芯片1和2之间直接连接)就停止了，所以往往难以采用具有小尺寸的模块衬底。通过采取措施，将模块衬底与进行了叠置的半导体芯片1和2进行相互偏离以使得中心位置左右偏离，并进一步地将它们进行堆积，从而可以首次采用具有小尺寸的模块衬底。
接下来，按照图4所示的流程图说明本发明的半导体器件4的制造方法。
首先，在图4的步骤S1，制备图5和图6中所示的模块衬底3。对于模块衬底3，在前表面(主表面)上沿多个侧301、304、306和308分别形成多个键合引线302、303、305、307和309。
接下来，在图4的步骤S2，如图7和图8所示，经由粘合剂(未示出)在模块衬底3的前表面上安装第一半导体芯片1。在第一半导体芯片1的主表面中形成集成的内部电路(第一电路)。沿第一半导体芯片1的多个侧100、102、104和107分别形成经由布线层与内部电路电连接的多个电极焊盘101、103、105、106和108。将第一半导体芯片1安装在其中中心线CL2偏离模块衬底的中心线CL1的位置中。即，安装第一半导体芯片1使得第一半导体芯片1的中心线CL2向模块衬底3的第二侧偏离，从而模块衬底3的第一侧301与第一半导体芯片1的第三侧100的间隙可以变得大于模块衬底3的第二侧306与第一半导体芯片1的第四侧104的间隙。
接下来，在图4的步骤S3，如图9和图10所示，经由粘合剂(未示出)将第二半导体芯片2安装在第一半导体芯片1上。在第二半导体芯片2的主表面中形成集成的内部电路(第二电路)。沿第二半导体芯片2的多个侧200、202和204分别形成经由布线层与内部电路电连接的多个电极焊盘201、203和205。将第二半导体芯片2安装在第一半导体芯片1上的其中中心线CL2偏离模块衬底的中心线CL1的位置处，换言之，使得其可以与第一半导体芯片1的中心线CL2重叠。因而，当在第二级之后层压半导体芯片2时，通过使各半导体芯片1和2的中心线作为对准标记而进行层压，使得上侧的半导体芯片的中心线可以与下侧的半导体芯片的中心线重叠，从而可以使得组装性变得容易。
然后，如图4的步骤S4所示，通过在热气氛中对安装有第一和第二半导体芯片1和2的模块衬底3进行烘焙处理，使上述粘合剂硬化。
接下来，在图4的步骤S5和S6中，如图11和图12所示，经由多个由导电部件构成的键合导线502、506、507和508分别将第一半导体芯片1的多个电极焊盘101、103、105、106和108与模块衬底3的多个键合引线303、305、307和309电连接。然后，分别通过多个由导电部件构成的键合导线501和505将第二半导体芯片2的多个电极焊盘201和203与模块衬底3的多个键合引线302和305电连接。分别通过多个由导电部件构成的键合导线500将第二半导体芯片2的多个电极焊盘205与第一半导体芯片1的多个电极焊盘105电连接。当在执行了上侧的半导体芯片2与模块衬底3的导线键合之后执行下侧的半导体芯片1与模块衬底3的导线键合时，先前所形成的导线与作为导线键合工具的毛细管的尖端接触，并有可能引起断开故障。于是如本发明那样，通过在执行了下侧的半导体芯片1与模块衬底3的导线键合之后执行上侧的半导体芯片2与模块衬底3的导线键合，可以抑制导线和毛细管的接触。这是因为在后形成的导线的环状比在前形成的导线的环状靠上。
接下来，在图4的步骤S7中，如图13所示，通过树脂600密封模块衬底3的前表面侧、第一半导体芯片1、第二半导体芯片2以及多个键合导线500、501、502、505、506、507和508，并且形成一个密封体。
然后在图4的步骤S8中，如图14所示，在模块衬底3的背表面侧中形成多个球电极601。尽管未示出，但多个球电极601分别经由形成在模块衬底3内部层中的布线层与当前形成在前表面上的多个键合引线302、303、305、307和309电连接。
在前述内容中，基于以上实施例具体说明了本发明人所完成的本发明，但本发明并不限于上述实施例，而是当然可以在不偏离本发明精神的限制下以各种方式进行变化和修改。
例如，第一和第二半导体芯片不局限于CCD摄像机的定时控制器和驱动器。它们可以是诸如液晶显示器的驱动器和显示控制器、存储器和存储控制器、微计算机、工作存储器之类的其它装置的组合。在半导体芯片的内部电路中，电路配置应当根据所关注的半导体芯片的功能来适当地确定。
并不局限于例如通过单个模制方法所进行的树脂密封，而是可以在将多个半导体芯片分别安装在具有多个产品形成区的模块衬底上之后，利用批量模制方法(MAP)将多个产品形成区成块放置并进行树脂密封。在这种情况下，在单个分离步骤中，通过划片刀切割并分离多个产品形成区，并且在与模块衬底的端部相同的位置中形成所需半导体器件的密封体的端部。

Claims (8)

1.一种半导体器件，包括：
模块衬底，其包括沿第一侧布置的多个第一键合引线、沿所述第一侧布置的比所述第一键合引线更靠近所述第一侧的多个第二键合引线以及沿与所述第一侧相对的第二侧布置的多个第三键合引线；
第一半导体芯片，其安装在所述模块衬底上方，并且其包括集成的第一电路、沿第三侧布置且耦合到所述第一电路的多个第一电极焊盘以及沿与所述第三侧相对的第四侧布置且耦合到所述第一电路的多个第二电极焊盘；
第二半导体芯片，其安装在所述第一半导体芯片上方，并且其包括集成的第二电路、沿第五侧布置且耦合到所述第二电路的多个第三电极焊盘以及沿与所述第五侧相对的第六侧布置且耦合到所述第二电路的多个第四电极焊盘；
第一导线，其分别电连接所述第一键合引线和其对应的所述第一电极焊盘；
第二导线，其分别电连接所述第二键合引线和其对应的所述第三电极焊盘；
第三导线，其分别电连接所述第三键合引线和其对应的所述第二电极焊盘；以及
第四导线，其分别电连接所述第二电极焊盘和其对应的所述第四电极焊盘；
其中，所述第三侧和所述第五侧靠近所述第一侧布置，所述第四侧和所述第六侧靠近所述第二侧布置，并且所述第一侧与所述第三侧的间隙大于所述第二侧与所述第四侧的间隙。
2.根据权利要求1所述的半导体器件，其中
所述第三侧与所述第五侧的间隙等于所述第四侧与所述第六侧的间隙。
3.根据权利要求2所述的半导体器件，其中
对于共享所述第四导线的所述第二电极焊盘和所述第四电极焊盘，其一方是输出端子，而另一方是对应的输入端子。
4.根据权利要求3所述的半导体器件，其中
所述第三键合引线的数目少于所述第一键合引线的数目。
5.一种半导体器件，包括：
模块衬底；
第一半导体芯片，安装在所述模块衬底上方，与所述模块衬底之间中心位置左右相互偏离，并且其中集成有第一电路；以及
第二半导体芯片，安装在所述第一半导体芯片上方并且其中集成有第二电路；
其中，在从所述偏离的第一半导体芯片的边缘到所述模块衬底的边缘的距离较短的一侧上，在所述第一半导体芯片上方的电极焊盘与相互对应的所述第二半导体芯片上方的电极焊盘通过导线直接连接；并且
在从所述偏离的第一半导体芯片的边缘到所述模块衬底的边缘的距离较长的一侧上，在所述第一半导体芯片上方的电极焊盘和在所述第二半导体芯片上方的电极焊盘与在所述模块衬底上方的对应键合引线通过导线连接。
6.根据权利要求5所述的半导体器件，其中
所述第二半导体芯片的中心位置与所述第一半导体芯片的中心位置不相互偏离。
7.根据权利要求6所述的半导体器件，其中
对于利用导线直接相互连接的在所述第一半导体芯片上方的电极焊盘和在所述第二半导体芯片上方的电极焊盘，其一方是输出端子，而另一方是对应的输入端子。
8.根据权利要求5所述的半导体器件，其中
在从所述偏离的第一半导体芯片的边缘到所述模块衬底的边缘的距离较短的一侧上，所述第一半导体芯片上方的电极焊盘和相互对应的所述模块衬底上方的键合引线通过导线连接。
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CN104299947B (zh) * 2013-07-19 2018-04-06 瑞萨电子株式会社 制造半导体器件的方法
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CN107622989B (zh) * 2016-07-15 2019-12-10 日月光半导体制造股份有限公司 半导体封装装置及其制造方法
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CN112309875A (zh) * 2020-11-02 2021-02-02 南方电网科学研究院有限责任公司 一种芯片封装方法

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