CN107622989A - 半导体封装装置及其制造方法 - Google Patents
半导体封装装置及其制造方法 Download PDFInfo
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- CN107622989A CN107622989A CN201710574710.9A CN201710574710A CN107622989A CN 107622989 A CN107622989 A CN 107622989A CN 201710574710 A CN201710574710 A CN 201710574710A CN 107622989 A CN107622989 A CN 107622989A
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- conductive layer
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Abstract
一种半导体封装装置包含第一裸片、粘合剂层和囊封剂层。所述第一裸片包括所述第一裸片的第一表面处的第一电极,和所述第一裸片的与所述第一裸片的所述第一表面相对的第二表面处的第二电极。所述粘合剂层安置于所述第一裸片的所述第一表面上。所述囊封剂层囊封所述第一裸片和所述粘合剂层,其中所述第二电极的大体上整个表面从所述囊封剂层暴露。
Description
相关申请的交叉参考
本申请主张2016年7月15日申请的第62/363,130号美国临时申请的权益和优先权,所述临时申请的内容以全文引用的方式并入本文中。
技术领域
本发明大体上涉及一种半导体封装装置及其制造方法。
背景技术
半导体装置(例如裸片或芯片)可附接到载体且由囊封剂囊封从而形成半导体装置封装。为促成小型化,腔可形成于载体中以容纳半导体装置。保护膜可层压到半导体装置和载体。可通过例如光刻技术、镀敷技术或其它适当技术形成于半导体装置上方的再分布结构可用于外部连接。然而,此制造半导体装置封装的工艺可能较昂贵。此外,此工艺可涉及极精确的对准和对齐技术。
发明内容
在一或多个实施例中,根据本发明的一个方面,提供一种半导体封装装置。所述半导体封装装置包含第一裸片、粘合剂层和囊封剂层。第一裸片包括安置在第一裸片的第一表面处的第一电极,和安置在第一裸片的与第一裸片的第一表面相对的第二表面处的第二电极。粘合剂层安置于第一裸片的第一表面上。囊封剂层囊封第一裸片和粘合剂层,其中第二电极的大体上整个表面从囊封剂层暴露。
在一或多个实施例中,根据本发明的另一方面,一种制造半导体封装装置的方法包含提供具有安置在其上的第一导电层的载体,以及经由第一粘合剂层将第一裸片的第一侧附接到所述载体,第一裸片包含安置在第一侧的第一电极和安置在与第一侧相对的第二侧的第二电极。所述方法进一步包含用囊封剂囊封第一裸片和第一粘合剂层使得第一裸片的第二电极的大体上整个表面从囊封剂暴露,以及移除所述载体。
附图说明
当结合附图阅读时,从以下详细描述最好地理解本发明的各方面。各种特征可能未按比例绘制,且所描绘的特征的尺寸可出于论述的清楚起见任意增大或减小。
图1A和图1B说明根据本发明的第一方面的半导体封装装置的一些实施例的横截面图。
图2A、图2B、图2C、图2D、图2E和图2F说明根据本发明的一些实施例的制造半导体封装装置的方法。
图3说明根据本发明的第二方面的半导体封装装置的一些实施例的横截面图。
图4A、图4B、图4C、图4D、图4E和图4F说明根据本发明的一些实施例的制造半导体封装装置的方法。
图5说明根据本发明的第三方面的半导体封装装置的一些实施例的横截面图。
图6A、图6B、图6C、图6D、图6E和图6F说明根据本发明的一些实施例的制造半导体封装装置的方法。
图7A和图7B说明根据本发明的第四方面的半导体封装装置的一些实施例的横截面图。
图8A、图8B、图8C、图8D、图8E、图8F和图8G说明根据本发明的一些实施例的制造半导体封装装置的方法。
图9说明根据本发明的第五方面的半导体封装装置的一些实施例的横截面图。
图10A、图10B、图10C、图10D、图10E、图10F和图10G说明根据本发明的一些实施例的制造半导体封装装置的方法。
贯穿图式和具体实施方式使用共同参考数字以指示相同或类似元件。根据以下结合附图作出的详细描述将容易地理解本发明。
具体实施方式
图1A说明根据本发明的第一方面的半导体封装装置1的一些实施例的横截面图。半导体封装装置1包含裸片10、粘合剂层11、导电层12、图案化导电层13、囊封剂层14、导电层15和图案化导电层16。
裸片10具有表面10a和与表面10a相对的另一表面10b。在一些实施例中,表面10a可被称为前侧,且表面10b可被称为背侧,然而,此描述仅为方便起见且并不希望限制表面10a、10b的任何方面。裸片10可包含半导体材料,例如硅(Si)和第III-V族材料(例如,包含周期表族III和V的元素的材料),且可掺杂有其它合适的材料。裸片10可包含半导体衬底、一或多个集成电路装置和一或多个上覆互连结构,所述集成电路装置可包含例如晶体管等有源装置,和/或例如电阻器、电容器、电感器等无源装置,或其组合。在一些实施例中,裸片10可为功率装置,例如功率晶体管、功率二极管或IGBT(绝缘栅双极晶体管)。与非功率装置(例如,逻辑组件和/或控制器)相比,功率装置可消耗较多电流或电力,且因此耗散较多热能。
裸片10可包含表面10a上或处的电极101,和表面10b上或处的电极102。电极101、102可实现与裸片10的外部电连通。在一些实施例中,电极101、102可包含接触件或垫片。在一些实施例中,一个以上电极101可安置于表面10a上。在一些实施例中,一个以上电极102可安置于表面10b上。电极101的大小可不同于电极102的大小。电极101的大小可具有大体上等于电极102的大小的大小。
粘合剂层11安置于裸片10的表面10a上,且可用以将裸片10附接到半导体封装装置1的其它部分(例如,附接到图案化导电层13)。在一些实施例中,粘合剂层11可为例如凝胶型或膜型粘合剂层等粘合剂层。粘合剂层11可包含热固性树脂。粘合剂层11可包含热塑性树脂。粘合剂层11可包含以下各者中的一或多者:树脂、聚酯树脂、聚醚树脂、环氧树脂和聚烯烃组合物。粘合剂层11可比裸片10厚。粘合剂层11可比裸片10薄,或与裸片10大体上一样厚。粘合剂层11可沿着裸片10的周长安置。粘合剂层11可界定可暴露电极101的一或多个开口或凹口。
导电层12安置于裸片10的表面10b上。导电层12为任选的。根据本发明的一些实施例,导电层12可省略。电极102可接触导电层12(例如,电极102的一部分可接触导电层12,或电极102的大体上整个表面(例如顶部表面)可接触导电层12)。在一些实施例中,导电层12可包含背侧金属层。在一些实施例中,与例如焊料结合或瞬变相液体结合(TLP)的一些实施方案(其中的每一者可产生较高电阻和热阻)相比,导电层12可用于实现改进的热和/或电传输特性。在一些实施例中,导电层12可操作为散热块或散热片或散热器。此外,提供导电层12的特定方法(例如镀敷)实现制造期间减小的热应力,因为举例来说,与焊接(其可在例如大于约170℃、例如大于约180℃、大于约190℃或大于约200℃的温度下执行)或TLP(其可在例如高达约450℃或更高的温度下执行)相比,可在中等温度(例如,小于约50摄氏度(℃)、例如小于约45℃、小于约40℃,或小于约35℃)下执行镀敷技术。此外,焊料或TLP回焊可致使裸片10移位,且借此增加未对准。例如当导电层12在电力或接地路径中或高电流路径中连接时,例如导电层12的较低电阻等改进的电传输特性可能是有益的。
囊封剂层14具有表面14a、表面14b和在表面14a、14b之间延伸的横向表面14c。在一些实施例中,囊封剂层14可包含(但不限于)具有填充剂的环氧树脂、模制化合物(例如,环氧模制化合物或其它模制化合物)、聚酰亚胺、酚化合物或材料、具有分散在其中的硅酮的材料,或其组合。
囊封剂层14可囊封裸片10、粘合剂层11和任选导电层12。电极102(例如电极102的顶部表面)可从囊封剂层14整体或部分暴露。举例来说,电极102的大体上整个表面(例如顶部表面)可从囊封剂层14暴露,使得电极102的顶部表面的至少90%从囊封剂层14暴露(例如,电极102的顶部表面的至少约92%、至少约95%、至少约98%或更多部分暴露)。此类暴露可实现电极102与半导体封装装置1的除囊封剂层14以外的部分或组件的电和/或热连通,所述部分或组件与囊封剂层14相比可具有更合乎需要的电和/或热特性(例如,在一些实施方案中,较低电阻和/或热阻)。在一些实施例中,电极102暴露于半导体封装装置1的具有较低电阻和/或热阻的其它部分或组件越多,则其间的电和热连通越强。
表面14a可与表面10a大体上共面,或可与粘合剂层11的底部表面大体上共面。在一些实施例中,表面14b可与裸片10的表面10b大体上共面,或与导电层12(例如,在包含导电层12的实施方案中)的表面大体上共面。在一些实施例中,粘合剂层11的一或多个表面可从表面14a凹进。在一些实施例中,表面10b和/或导电层12的顶部表面可从表面14b凹进。
导电层15安置于囊封剂层14和裸片10上方,且可通过例如钛-铜或无电铜接种而溅镀或接种。导电层15还可镀敷到目标厚度(例如,约25μm、约50μm、约75μm,或另一合适的厚度)。在一些实施例中,导电层15可包含铜(Cu)。在一些实施例中,导电层12省略,且导电层15提供到裸片10和/或电极102的电和/或热连通。在一些实施例中,导电层15帮助以比类似定位的囊封剂层14(例如,比囊封剂层14,条件是其类似定位)高的速率耗散由裸片10产生的热。也就是说,导电层15可充当散热片。在其中导电层12省略且电极102直接接触导电层15的实施例中,电流和/或热可在裸片10和导电层15之间传递的速率与电极102和导电层15之间的直接接触的面积或量成正相关。在一些实施例中,导电层15覆盖电极102的大体上整个顶部表面。在一些实施例中,导电层15的侧表面与囊封剂层14的横向表面14c大体上共面。
晶种层151可安置于囊封剂层14和导电层15之间。根据本发明的一些实施例(例如,如图1B中展示的半导体装置1b中),晶种层151可省略。在一些实施例中,晶种层151接触导电层12。晶种层151是导电的,且可包含(例如)Cu或钛-铜合金(例如TiCu)。导电层15的制造可由晶种层151促进。导电层15和晶种层151可包含大体上相同材料,在此情况下其间的边界可能不容易辨别。导电层15和晶种层151可包含不同材料。
图案化导电层16安置于图案化导电层13上。图案化导电层16可包含金属,例如铜、铝、银或金。图案化导电层16可包含第一部分16v和第二部分16t。第一部分16v形成于粘合剂层11中的一或多个开口或凹口中,且提供到电极101的电和/或热连通,电极101通过开口或凹口从粘合剂层11暴露。在一些实施例中,第一部分16v可包含导电通孔或导电互连。在一些实施例中,第二部分16t可包含安置于半导体封装装置1上的一或多个迹线。
晶种层161形成或安置于暴露的电极101和图案化导电层16之间。晶种层161安置于粘合剂层11和图案化导电层16之间。晶种层161安置于图案化导电层13和图案化导电层16之间。根据本发明的一些实施例(例如,如图1B中展示的半导体装置1b中),晶种层161可省略。晶种层161可包含金属,例如铜、铝、银或金,且可包含促进图案化导电层16的制造的任何合适的材料。在一些实施例中,图案化导电层13、图案化导电层16和/或晶种层161可包含大体上相同材料,在此情况下相同材料的层之间的边界可能不容易辨别。图案化导电层13、图案化导电层16和/或晶种层161还可充当散热片,且合适的材料(例如Cu)可包含在图案化导电层16和/或晶种层161中以帮助实现散热片特性。
图2A、图2B、图2C、图2D、图2E和图2F说明根据本发明的一些实施例的制造半导体封装装置的方法。
参看图2A,提供载体299,且导电层23'安置于载体299上。载体299可包含层压物、层或堆叠,例如铜/铝/铜堆叠或铜/镍/铁合金/铜堆叠。堆叠可容易地剥离或以其它方式移除。载体299可具有低热膨胀系数(CTE)。导电层23'可包含任何合适的导电材料,例如铝、铜、银或金。导电层23'可经(例如)镀敷或溅镀。
参看图2B,提供裸片20、粘合剂层21和导电层22。裸片20具有表面20a和与表面20a相对的表面20b。至少一个电极201提供在表面20a上或处,且至少一个电极202提供在表面20b上或处。在一些实施例中,导电层22可省略。电极201的大小可与电极202的大小大体上相同。
参看图2C,裸片20和导电层22通过粘合剂层21附接到载体299。在一些实施例中,粘合剂层21安置于导电层23'或载体299上,且接着裸片20和导电层22安置于粘合剂层21上。在一些实施例中,裸片20安置于粘合剂层21上,且接着导电层22安置于裸片20上。可另外或替代地执行此过程的其它排列。在一些实施例中,导电层22可为背侧金属层,且可包含任何合适的金属、合金或其组合,例如镍-银或铜-镍。导电层22可通过电镀、溅镀或合适的技术安置,或可作为金属薄片或膜安置于裸片20上。
尽管图2A、图2B和图2C展示裸片20、粘合剂层21、导电层22和导电层23'安置于载体299的一侧上,但其中的任一者可使用类似或不同技术安置于载体299的相对侧上,或载体299的两侧上。
参看图2D,提供包含表面24a和与表面24a相对的表面24b的囊封剂层24以囊封裸片20、粘合剂层21和导电层22。如图2D中所展示,电极202至少部分从囊封剂层24暴露。在一些实施例中,电极202的大体上全部从囊封剂层24暴露。在一些实施例中,表面24b可与导电层22的顶部表面或裸片20的表面20b大体上共面。在一些实施例中,导电层22的顶部表面可凹进到表面24b下方。裸片20由囊封剂层24(例如,由模制化合物)囊封,且因此在一些实施例中可省略其它保护膜(例如预浸体保护膜)的层压。
裸片附接操作可涉及高温(例如以固化粘合剂层21)。因为裸片20在已附接之后囊封,所以囊封剂层24并不直接经受高温,且因此并不经历比例如囊封剂层24的材料的玻璃转化温度(Tg)高的温度。因此,囊封剂层24可能不软化且可在后续制造工艺中牢固地固持经囊封裸片20,借此减小裸片20的位移并改进其与半导体封装装置的其它部分的对准,以及其对齐。
参看图2E,移除载体299。形成暴露对应电极201的至少一个开口26o(例如,粘合剂层21中和/或导电层23'中)。开口26o可通过移除导电层23'的一部分且接着移除粘合剂层21的一部分而形成。所述两个部分可在一个、两个或两个以上阶段中移除。开口26o可例如通过光刻技术、激光烧蚀、蚀刻和/或钻孔而形成。因为导电层23'的材料可能不同于粘合剂层21的材料,所以可能有利的是采用不同技术移除不同层的部分从而形成开口26o。在开口26o形成之后,现经图案化的导电层23'被称作图案化导电层23。
开口26o经形成以在裸片20已附接之后暴露电极201。以此方式,可较好地控制电极201暴露的位置,借此改进对准和对齐。
然后,导电层可形成于囊封剂层24上,且图案化导电层可形成于图案化导电层23上以到达例如如图1B中所展示的半导体封装装置1b。导电层可通过任何合适的技术形成,例如溅镀/填充。图案化导电层可通过合适的技术形成,例如溅镀,继之以合适的图案化技术,例如光刻、钻孔、激光烧蚀和蚀刻(例如,盖孔蚀刻剥离(tent etch stripping)和/或剥离闪光蚀刻(strip flash etching))。
图2F说明可在图2E中说明的阶段之后执行的另一阶段。可形成晶种层251和/或晶种层261。晶种层251、261是导电的,且可促进后续制造工艺,例如其上导电层的形成。如图2F中所展示,晶种层261可形成于粘合剂层21和/或图案化导电层23的侧壁上和/或形成于暴露的电极201上。
然后,导电层可形成于晶种层251上,且图案化导电层可形成于晶种层261上以到达例如如图1A中所展示的半导体封装装置1。导电层可通过任何合适的技术形成,例如电镀或无电镀敷(晶种层251可促进的)和溅镀。图案化导电层可通过合适的技术形成,例如电镀或无电镀敷(晶种层261可促进的)和溅镀/填充,继之以合适的图案化技术,例如光刻、钻孔、激光烧蚀和蚀刻(例如,盖孔蚀刻剥离和/或剥离闪光蚀刻)。在一些实施例中,导电层和图案化导电层的任何或所有部分(例如通孔和迹线)的形成可在单一操作中执行。
图3说明根据本发明的第二方面的半导体封装装置3的一些实施例的横截面图。半导体封装装置3包含裸片10、粘合剂层11、导电层12、图案化导电层13、囊封剂层14、导电层35和图案化导电层36。
图3中展示的半导体封装装置3和图1A中展示的半导体封装装置1之间的一个差异是,半导体封装装置3包含导电互连353,其电连接导电层35和图案化导电层36。导电互连353的数目和宽度可设定成适当值以例如提供例如导电层35和图案化导电层36之间的所希望水平的电和/或热连通(例如电流和热耗散)。
晶种层351可安置于囊封剂层14和导电层35之间,或根据本发明的一些实施例可省略。在一些实施例中,晶种层351接触导电层12。晶种层351是导电的且可包含Cu或TiCu。导电层35的制造可由晶种层351促进。导电层35和晶种层351可包含大体上相同材料,在此情况下其间的边界可能不容易辨别。导电层35和晶种层351可包含不同材料。
晶种层352可安置于囊封剂层14和导电互连353之间,或根据本发明的一些实施例可省略。导电互连353的制造可由晶种层352促进。晶种层352是导电的且可包含Cu或TiCu。晶种层351和352可包含大体上相同材料,或不同材料。
图案化导电层36安置于图案化导电层13上。图案化导电层36可包含金属,例如铜、铝、银或金。图案化导电层36可包含第一部分36v和第二部分36t。第一部分36v安置在粘合剂层11的开口中,且实现到从粘合剂层11暴露的电极101的电和/或热连通。在一些实施例中,第一部分36v可包含导电通孔或导电互连。在一些实施例中,第二部分36t可包含安置于半导体封装装置3上的一或多个迹线。
晶种层361形成或安置于暴露的电极101和图案化导电层36之间。晶种层361安置于粘合剂层11和图案化导电层36之间。晶种层361安置于图案化导电层13和图案化导电层36之间。根据本发明的一些实施例,晶种层361可省略。晶种层361可包含金属,例如铜、铝、银或金,且可包含促进图案化导电层36的制造的任何合适的材料。在一些实施例中,图案化导电层13、图案化导电层36和/或晶种层361可包含大体上相同材料,在此情况下相同材料的层之间的边界可能不容易辨别。
图4A、图4B、图4C、图4D、图4E和图4F说明根据本发明的一些实施例的制造半导体封装装置的方法。
图4A、图4B、图4C和图4D中展示的过程类似于图2A、图2B、图2C和图2D中展示的过程,且因此不详细地描述。
参看图4E,移除载体299。至少一个开口45o形成于囊封剂层24和导电层23'中,且至少一个开口46o形成于粘合剂层21和导电层23'中。在开口45o和46o形成之后,导电层23'经图案化且因此被称作图案化导电层23。开口45o可通过移除导电层23'的一部分以及移除囊封剂层24的一部分而形成。所述两个部分可在一个、两个或两个以上阶段中移除。开口46o可通过移除导电层23'的一部分且接着移除粘合剂层21的一部分而形成。所述两个部分可在一个、两个或两个以上阶段中移除。开口45o和46o可通过例如光刻技术、激光烧蚀、蚀刻和/或钻孔形成。因为导电层23'、囊封剂层24和粘合剂层21的材料可能彼此不同,所以可能有利的是采用不同技术移除不同层的部分从而形成开口45o和46o。
开口46o经形成以在裸片20已附接之后暴露电极201。以此方式,可较好地控制电极201暴露的位置,借此改进对准和对齐。
参看图4F,可形成晶种层451、晶种层452和/或晶种层461。晶种层451、452、461是导电的且可促进后续制造工艺,例如其上导电层的形成。如图4F中所展示,晶种层461可形成于粘合剂层21和/或图案化导电层23的侧壁上和/或形成于暴露的电极201上。
然后,导电层可形成于晶种层451上,图案化导电层可形成于晶种层461上,且导电互连可形成于开口45o中以到达例如如图3中所展示的半导体封装装置3。导电层和导电互连可通过任何合适的技术形成,例如电镀或无电镀敷(晶种层451、452可促进的)和溅镀/填充。图案化导电层可通过合适的技术形成,例如电镀或无电镀敷(晶种层461可促进的)和溅镀/填充,继之以合适的图案化技术,例如光刻、钻孔、激光烧蚀和蚀刻(例如,盖孔蚀刻剥离和/或剥离闪光蚀刻)。在一些实施例中,导电层、图案化导电层的任何或所有部分(例如通孔和迹线)和导电互连的形成可在单一操作中执行。
在一些实施例中,不形成晶种层451、452、461,在此情况下导电层、图案化导电层和导电互连可通过溅镀继之以合适的图案化技术而形成。
图5说明根据本发明的第三方面的半导体封装装置5的一些实施例的横截面图。半导体封装装置5包含裸片50、粘合剂层51、导电层52、图案化导电层53、囊封剂层54、导电层55、图案化导电层56、裸片58和粘合剂层59。尽管图5描绘两个裸片50、58,但半导体封装装置5可包含两个以上裸片,例如三个、四个、五个、六个、七个或七个以上。
裸片50可包含安置于裸片50的表面50a上或处的电极501,和安置于表面50b上或处的电极502。电极501、502可实现与裸片50的外部电连通。在一些实施例中,电极501、502可包含接触件或垫片。在一些实施例中,一个以上电极501可安置于表面50a上或处。在一些实施例中,一个以上电极502可安置于表面50b上或处。电极501的大小可不同于电极502的大小。电极501的大小可与电极502的大小大体上相同。
裸片50具有表面50a和与表面50a相对的另一表面50b。在一些实施例中,表面50a可被称为前侧,且表面50b可被称为背侧。然而,此描述仅为方便起见,且不希望限制表面50a、50b的任何方面。裸片50可包含半导体材料,例如Si和III-V材料,且可掺杂有其它合适的材料。裸片50可包含半导体衬底、一或多个集成电路装置和一或多个上覆互连结构。集成电路装置可包含例如晶体管等有源装置,和/或例如电阻器、电容器、电感器等无源装置,或其组合。在一些实施例中,裸片50可包含功率装置,例如功率晶体管、功率二极管或IGBT。与非功率装置(例如逻辑组件和/或控制器)相比,功率装置可消耗更多电流或电力且因此耗散更多热能。
粘合剂层51安置于裸片50的表面50a上,且可用以将裸片50附接到半导体封装装置5的其它部分(例如,附接到图案化导电层53)。在一些实施例中,粘合剂层51可以是例如凝胶型或膜型粘合剂层等粘合剂层。粘合剂层51可包含热固性树脂。粘合剂层51可包含热塑性树脂。粘合剂层51可包含以下各者中的一或多者:树脂、聚酯树脂、聚醚树脂、环氧树脂和聚烯烃组合物。粘合剂层51可比裸片50厚或薄。粘合剂层51可安置于裸片50的周长内。粘合剂层51可包含可暴露电极501的一或多个开口。
导电层52安置于裸片50的表面50b上。导电层52为任选的。根据本发明的一些实施例,导电层52可省略。电极502可接触导电层52(例如,电极502的一部分可接触导电层52,或电极502的大体上整个表面(例如顶部表面)可接触导电层52)。在一些实施例中,导电层52可以是背侧金属层。在一些实施例中,例如与焊料结合或TLP(其中的每一者包含较高电阻和热阻)相比,导电层52可用于提供改进的热和/或电传输特性。在一些实施例中,导电层52可操作为散热块或散热片或散热器。此外,提供导电层52的一些方法(例如镀敷)实现制造期间减小的热应力,因为举例来说,与焊接(其可在例如大于约170℃、例如大于约180℃、大于约190℃或大于约200℃的温度下执行)或TLP(其可在例如高达约450℃或更高的温度下执行)相比,可在中等温度(例如,小于约50度(℃)、例如小于约45℃、小于约40℃,或小于约35℃)下执行镀敷技术。此外,焊料或TLP回焊可致使裸片50移位,且借此增加未对准。例如当导电层52在电力或接地路径中或高电流路径中连接时,例如导电层52的较低电阻等改进的电传输特性可能是有益的。
裸片58具有表面58a和与表面58a相对的另一表面58b。在一些实施例中,表面58a可被称为前侧,且表面58b可被称为背侧,然而,此描述仅为方便起见且并不希望限制表面58a、58b的任何方面。裸片58可包含半导体材料,例如Si和第III-V族材料,且可掺杂有所关注的其它材料。裸片58可包含半导体衬底、一或多个集成电路装置和一或多个上覆互连结构;所述集成电路装置可包含例如晶体管等有源装置,和/或例如电阻器、电容器、电感器等无源装置,或其组合。在一些实施例中,裸片58可以是非功率装置,例如逻辑组件和/或控制器。与功率装置(例如功率晶体管、功率二极管或IGBT)相比,非功率装置可消耗较少电流或电力且因此耗散较少热能。
裸片58可包含安置于表面58a上或处的电极581。电极581可实现与裸片58的外部电连通。在一些实施例中,电极581可包含接触件或垫片。在一些实施例中,一个以上电极581可安置于表面58a上或处。
囊封剂层54具有表面54a、与表面54a相对的表面54b,以及在表面54a、54b之间延伸的横向表面54c。在一些实施例中,囊封剂层54可包含(但不限于)具有填充剂的环氧树脂、模制化合物(例如,环氧模制化合物或其它模制化合物)、聚酰亚胺、酚化合物或材料、具有分散在其中的硅酮的材料,或其组合。
囊封剂层54可囊封裸片50、粘合剂层51、导电层52、裸片58和粘合剂层59。电极502(例如电极502的顶部表面)可从囊封剂层54整体或部分暴露。此类暴露可实现电极502与半导体封装装置5的除囊封剂层54以外的部分或组件成电和/或热连通,所述部分或组件与囊封剂层54相比可具有更合乎需要的电和/或热特性(例如,在一些实施方案中,较低电阻和/或热阻)。在一些实施例中,电极502暴露于半导体封装装置5的具有较低电阻和/或热阻的其它部分或组件越多,则越有助于其间的电和热连通。
表面54a可与表面50a大体上共面,或可与粘合剂层51的底部表面大体上共面。在一些实施例中,表面54b可与裸片50的表面50b大体上共面,或与导电层52的表面大体上共面(如果导电层52包含在半导体封装装置5中)。在一些实施例中,粘合剂层51和59的一或多个表面可从表面54a凹进。在一些实施例中,表面50b和/或导电层52的表面可从表面54b凹进。在一些实施例中,表面58b安置在表面54b下方或下部。
导电层55安置于囊封剂层54、裸片50和裸片58上方,且可例如通过钛-铜或无电铜接种而溅镀或接种。导电层55还可镀敷到目标厚度(例如,约25μm、约50μm、约75μm,或另一合适的厚度)。在一些实施例中,导电层55可包含Cu。在一些实施例中,省略导电层52,且导电层55提供到裸片50和/或电极502的电和/或热连通。在一些实施例中,导电层55帮助以比类似定位的囊封剂层(例如,比囊封剂层54,条件是其类似定位)高的速率耗散由裸片50产生的热。也就是说,导电层55可充当散热片。在其中导电层52省略且电极502直接接触导电层55的实施例中,电流和/或热可在裸片50和导电层55之间传递的速率与电极502和导电层55之间的直接接触的面积或量成正相关。
晶种层551可安置于囊封剂层54和导电层55之间。根据本发明的一些实施例,晶种层551可省略。在一些实施例中,晶种层551接触导电层52。晶种层551是导电的且可包含Cu或TiCu。导电层55的制造可由晶种层551促进。导电层55和晶种层551可包含大体上相同材料,在此情况下其间的边界可能不容易辨别。导电层55和晶种层551可包含不同材料。
图案化导电层56安置于图案化导电层53上。图案化导电层56可包含金属,例如铜、铝、银或金。图案化导电层56可包含第一部分56v和第二部分56t。第一部分56v形成于由粘合剂层51和59界定的开口或凹口中,且提供到电极501和581的电和/或热连通,电极501和581分别从粘合剂层51和59暴露。在一些实施例中,第一部分56v可包含导电通孔或导电互连。在一些实施例中,第二部分56t可包含安置于半导体封装装置5上的一或多个迹线。在一些实施例中,图案化导电层53和/或图案化导电层56提供裸片50和58之间的电和热连通。
晶种层561形成或安置于暴露的电极501和图案化导电层56之间和/或暴露的电极581和图案化导电层56之间。晶种层561安置于粘合剂层51和59与图案化导电层56之间。晶种层561安置于图案化导电层53和图案化导电层56之间。根据本发明的一些实施例,晶种层561可省略。晶种层561可包含金属,例如铜、铝、银或金,且可包含促进图案化导电层56的制造的任何材料。在一些实施例中,图案化导电层53、图案化导电层56和/或晶种层561可包含大体上相同材料,在此情况下相同材料的层之间的边界可能不容易辨别。图案化导电层53、图案化导电层56和/或晶种层561还可充当散热片,且合适的材料(例如Cu)可包含在图案化导电层53、图案化导电层56和/或晶种层561中以帮助实现散热片特性。
图6A、图6B、图6C、图6D、图6E和图6F说明根据本发明的一些实施例的制造半导体封装装置的方法。
参看图6A,提供载体699,且导电层63'安置于载体699上。载体699可包含层压物、层或堆叠,例如铜/铝/铜堆叠或铜/镍/铁合金/铜堆叠。堆叠可容易地剥离或以其它方式移除。载体699可具有低CTE。导电层63'可包含任何合适的导电材料,例如铝、铜、银或金。导电层63'可经(例如)镀敷或溅镀。
参看图6B,提供裸片60、粘合剂层61和导电层62。还可提供裸片68和粘合剂层69。裸片60具有表面60a,以及与表面60a相对的表面60b。至少一个电极601提供在表面60a上或处,且至少一个电极602提供在表面60b上或处。在一些实施例中,导电层62可省略。电极601的大小可与电极602的大小大体上相同。在其它实施例中,电极601的大小可不同于电极602的大小。裸片68具有表面68a和与表面68a相对的表面68b。至少一个电极681提供在表面68a上或处。
参看图6C,裸片60和导电层62通过粘合剂层61附接到载体699。裸片68通过粘合剂层69附接到载体699。在一些实施例中,粘合剂层61和69安置于导电层63'或载体699上,且接着裸片60和68以及导电层62分别安置于粘合剂层61和69上。在一些实施例中,裸片60安置于粘合剂层61上,且接着导电层62安置于裸片60上。可另外或替代地执行此过程的其它排列。在一些实施例中,导电层62可以是背侧金属层,且可包含任何合适的金属、合金或其组合,例如镍-银或铜-镍。导电层62可通过电镀、溅镀或合适的技术安置,或可作为金属薄片或膜安置于裸片60上。
尽管图6A、图6B和图6C展示裸片60、粘合剂层61、导电层62、导电层63'、裸片68和粘合剂层69安置于载体699的一侧上,但其中的任一者可使用类似或不同技术安置于载体699的相对侧上,或载体699的两侧上。
参看图6D,提供具有表面64a和表面64b的囊封剂层64以囊封裸片60、粘合剂层61、导电层62、裸片68和粘合剂层69。如图6D中所展示,电极602从囊封剂层64至少部分暴露。在一些实施例中,电极602的顶部表面的大体上全部从囊封剂层64暴露。在一些实施例中,表面64b可与导电层62的顶部表面或裸片60的表面60b大体上共面。在一些实施例中,导电层62可凹进到表面64b下方。在一些实施例中,表面68b在表面64b下方或下部。裸片60和68由囊封剂层64(例如,由模制化合物)囊封,且因此在一些实施例中可省略其它保护膜(例如预浸体保护膜)的层压。
裸片附接操作可涉及高温(例如,以固化粘合剂层61和69)。因为裸片60和68在已附接之后囊封,所以囊封剂层64并不直接经受固化粘合剂层61和69的过程中所涉及的高温,且因此并不直接经受比例如囊封剂层64的材料的玻璃转化温度(Tg)高的温度。换句话说,囊封剂层64可能不软化且可在后续制造工艺中牢固地固持经囊封裸片60和68,借此减小裸片60和68的位移并改进其与半导体封装装置的其它部分的对准,以及其对齐。
参看图6E,移除载体699。形成分别暴露电极601和681的至少两个开口66o。开口66o可通过移除导电层63'的一部分且接着移除粘合剂层61和69的一部分而形成。所述部分可在一个、两个或两个以上阶段中移除。开口66o可通过例如光刻技术、激光烧蚀、蚀刻和/或钻孔而形成。因为导电层63'的材料可能不同于粘合剂层61和69的材料,所以可能有利的是采用不同技术移除不同层的部分从而形成开口66o。在开口66o形成之后,现经图案化的导电层63'被称作图案化导电层63。
开口66o经形成以在裸片60和68已经附接之后暴露电极601和681。以此方式,可较好地控制电极601和681暴露的位置,借此改进对准和对齐。
参看图6F,可形成晶种层651和/或晶种层661。晶种层651、661是导电的且可促进后续制造工艺,例如其上导电层的形成。如图6F中所展示,晶种层661可形成于粘合剂层61、69和/或图案化导电层63的侧壁上和/或形成于暴露的电极601、681上。
然后,导电层可形成于晶种层651上,且图案化导电层可形成于晶种层661上以到达例如如图5中所展示的半导体封装装置5。导电层可通过任何合适的技术形成,例如电镀或无电镀敷(晶种层651可促进的)和溅镀。图案化导电层可通过合适的技术形成,例如电镀或无电镀敷(晶种层661可促进的)和溅镀/填充,继之以合适的图案化技术,例如光刻、钻孔、激光烧蚀和蚀刻(例如,盖孔蚀刻剥离和/或剥离闪光蚀刻)。在一些实施例中,导电层和图案化导电层的任何或所有部分(例如通孔和迹线)的形成可在单一操作中执行。
图7A说明根据本发明的一些实施例的半导体封装装置7的横截面图。半导体封装装置7包含裸片50、粘合剂层51、导电层52、图案化导电层53、囊封剂层54、导电层55、图案化导电层56、裸片58、粘合剂层59、晶种层552和导电互连553。
图5中展示的半导体封装装置5和图7A中展示的半导体封装装置7之间的一个差异是导电互连553,其电连接导电层55和图案化导电层56。包含在半导体封装装置7中的导电互连553的数目和宽度可设定成适当值以例如提供例如导电层55和图案化导电层56之间的所希望水平的电和/或热连通(例如电流和热耗散)。
在一些实施例中,晶种层552和导电互连553包含大体上相同材料,在此情况下其间的边界可能不容易辨别(例如,图7A中的虚线矩形中的区在组成和/或粗糙度方面可能大体上均质)。
参看图7B,半导体封装装置7b类似于半导体封装装置7,但包含互连结构553'而非互连结构553,且包含晶种层552'而非晶种层552。在一些实施例中,晶种层552'、导电互连553'、图案化导电层53、晶种层561、图案化导电层56全部包含大体上相同材料,在此情况下其间的边界可能不容易辨别(例如,图7B中的虚线矩形中的区在组成和/或粗糙度方面可能大体上均质)。
图8A、图8B、图8C、图8D、图8E和图8F说明根据本发明的一些实施例的制造半导体封装装置的方法。
图8A、图8B、图8C和图8D中展示的过程类似于图6A、图6B、图6C和图6D中展示的过程,且因此不详细地描述。
参看图8E,移除载体699。至少一个开口65o形成于囊封剂层64和导电层63'中。分别暴露电极601和681的至少两个开口66o形成于粘合剂层61、69和导电层63'中。在导电层63'中形成开口导致图案化导电层,其将在本文被称作导电层63。可通过移除导电层63'的一部分且移除囊封剂层64的一部分而形成开口65o。可通过移除导电层63'的一部分且接着移除粘合剂层61和69的一部分而形成开口66o。所述部分可在一个、两个或两个以上阶段中移除。开口65o、66o可通过例如光刻技术、激光烧蚀、蚀刻和/或钻孔而形成。因为导电层63'、粘合剂层61、69和囊封剂层64的材料可能彼此不同,所以可能有利的是采用不同技术移除不同层的部分从而形成开口65o、66o。在开口65o、66o形成之后,导电层63'变为图案化导电层,其在本文被称作图案化导电层63。
参看图8F,可形成晶种层651、晶种层652和/或晶种层661。包含在图8F中展示的晶种层651、661中的材料和施加图8F中展示的晶种层651、661的阶段类似于上文参看图6F所描述,且因此不详细地描述。包含在图8F中展示的晶种层652中的材料和施加图8F中展示的晶种层652的阶段类似于上文参考图4F中展示的晶种层452所描述,且因此不详细地描述。
然后,导电层可形成于晶种层651上,图案化导电层可形成于晶种层661上,且导电互连可形成于开口65o中以到达例如如图7A中所展示的半导体封装装置7。导电层和导电互连可通过任何合适的技术形成,例如电镀或无电镀敷(晶种层651、652可促进的)和溅镀。。图案化导电层可通过合适的技术形成,例如电镀或无电镀敷(晶种层661可促进的)和溅镀/填充,继之以合适的图案化技术,例如光刻、钻孔、激光烧蚀和蚀刻(例如,盖孔蚀刻剥离和/或剥离闪光蚀刻)。
图8G中展示的过程可例如在图8A、图8B、图8C和图8D中展示的过程之后执行,以制造根据本发明的一些实施例的半导体封装装置。
图8G展示类似于图8E中展示的过程的过程,但不同之处在于:移除载体699之后,至少一个开口65o1形成于囊封剂层64中,且无开口形成于导电层63'中。分别暴露电极601和681的至少两个开口66o形成于粘合剂层61、69和导电层63'中。随后,可形成晶种层651、晶种层652'和/或晶种层661。包含在图8G中的晶种层651、661中的材料和施加图8G中的晶种层651、661的阶段类似于上文参看图8F所描述,且因此不详细地描述。包含在图8G中的晶种层652'中的材料和施加图8G中的晶种层652'的阶段类似于上文相对于图8F中展示的晶种层652所描述,且因此不详细地描述。
然后,导电层可形成于晶种层651上,图案化导电层可形成于晶种层661上,且导电互连可形成于开口65o1中以到达例如如图7B中所展示的半导体封装装置7b。导电层、图案化导电层的任何或所有部分(例如通孔和迹线)和导电互连的形成可在单一操作中执行。
图9说明根据本发明的第五方面的半导体封装装置9的一些实施例的横截面图。半导体封装装置9在一些方面中类似于半导体封装装置7。下文描述一些差异。半导体封装装置9包含导电层95、图案化导电层93、晶种层951和晶种层952。
导电层95包含突出部953。图案化导电层93包含突出部931。在一些实施例中,突出部931为立柱。晶种层951的形状不同于晶种层551以便容纳突出部953。在当前描述的实施例中,突出部931和囊封剂层54之间不存在晶种层。在其中导电层95、晶种层951、图案化导电层93、晶种层561和图案化导电层56包含大体上相同材料的一些实施例中,那些部分之间的边界可能不容易辨别(例如,图9中展示的虚线矩形9A中的区可能在组成和/或粗糙度方面大体上均质)。
图10A、图10B、图10C、图10D、图10E、图10F和图10G说明根据本发明的一些实施例的制造半导体封装装置的方法。此方法在一些方面类似于图6A、图6B、图6C、图6D、图6E和图6F中展示的方法。下文描述一些差异。
参看图10A,导电层1003'提供在载体699上。参看图10B,突出部(立柱)1032形成于图案化导电层1003'上。在一些实施例中,导电层1003'和突出部1032为一体式(例如一体地形成)且同时安置在载体699上。在一些实施例中,突出部(立柱)1032是导电的。
参看图10C和图10D,裸片60、粘合剂层61、任选导电层62、裸片68和粘合剂层69提供在导电层1003'上。在一些实施例中,突出部(立柱)1032可帮助确定制造工艺期间裸片60、68的位置且改进其对齐。
参看图10E,囊封剂层64经形成且囊封突出部1032。
参看图10F,开口1005o形成于囊封剂层64中以暴露突出部1032。在包含一个以上突出部1032的实施例中,所形成的开口1005o的总数可对应于突出部1032的总数。
参看图10G,晶种层1051、1052形成于囊封剂层64上。晶种层1052形成于开口1005o中。至少一个开口66o形成于导电层1003'中和粘合剂层61中以暴露裸片60的至少一个电极。导电层1003'在开口66o形成之后经图案化,且在本文被称作图案化导电层1003。晶种层661可视情况形成于图案化导电层1003上。
然后,具有突出部的导电层可形成于晶种层1051上,且图案化导电层可形成于晶种层661上以到达例如如图9中所展示的半导体封装装置9。具有突出部的导电层可通过任何合适的技术形成,例如电镀或无电镀敷(晶种层1051、1052可促进的)和溅镀。图案化导电层可通过合适的技术形成,例如电镀或无电镀敷(晶种层661可促进的)和溅镀/填充,继之以合适的图案化技术,例如光刻、钻孔、激光烧蚀和蚀刻(例如,盖孔蚀刻剥离和/或剥离闪光蚀刻)。在一些实施例中,导电层和图案化导电层的任何或所有部分(例如通孔和迹线)的形成可在单一操作中执行。
尽管在制造具有一个以上裸片的半导体封装装置的方法中说明突出部或立柱,但突出部或立柱也可适于形成具有单一裸片的半导体封装装置。
如本文中所使用,术语“近似”、“大体上”、“大体”和“约”用以描述和解释小的变化。当与事件或情形结合使用时,所述术语可以指其中事件或情形明确发生的情况以及其中事件或情形极接近于发生的情况。举例来说,当结合数值使用时,所述术语可指代小于或等于所述数值的±10%的变化范围,例如小于或等于±5%、小于或等于±4%、小于或等于±3%、小于或等于±2%、小于或等于±1%、小于或等于±0.5%、小于或等于±0.1%,或小于或等于±0.05%。举例来说,如果两个数值之间的差值小于或等于所述值的平均值的±10%(例如小于或等于±5%、小于或等于±4%、小于或等于±3%、小于或等于±2%、小于或等于±1%、小于或等于±0.5%、小于或等于±0.1%,或小于或等于±0.05%),那么可认为所述两个数值“大体上”或“大约”相同。举例来说,“大体上”平行可指相对于0°的小于或等于±10°的角变化范围,例如小于或等于±5°、小于或等于±4°、小于或等于±3°、小于或等于±2°、小于或等于±1°、小于或等于±0.5°、小于或等于±0.1°,或小于或等于±0.05°。举例来说,“大体上”垂直可指相对于90°的小于或等于±10°的角变化范围,例如小于或等于±5°、小于或等于±4°、小于或等于±3°、小于或等于±2°、小于或等于±1°、小于或等于±0.5°、小于或等于±0.1°,或小于或等于±0.05°。
如果两个表面之间的位移不大于5μm、不大于2μm、不大于1μm或不大于0.5μm,那么可认为这两个表面是共面的或大体上共面。
如本文所使用,术语“导电(conductive)”、“导电(electrically conductive)”和“电导率”指代运送电流的能力。导电材料通常指示展现对电流流动极少对抗或无对抗的那些材料。电导率的一个量度是西门子/米(s/m)。通常,导电材料是电导率大于近似104S/m(例如,至少105S/m或至少106S/m)的一种材料。材料的电导率有时可随温度而变化。除非另外指定,否则材料的电导率是在室温下测量。
如本文所用,除非上下文另外明确规定,否则单数术语“一(a/an)”和“所述(the)”包含多个指代物。在一些实施例的描述中,提供于另一组件“上”或“上方”的组件可涵盖前一组件直接在后一组件上(例如,与后一组件物理接触)的情况,以及一或多个介入组件位于前一组件与后一组件之间的情况。
虽然已参考本发明的特定实施例描述及说明本发明,但这些描述及说明并不限制本发明。所属领域的技术人员可清楚地理解,可进行各种改变,且可在实施例内替代等效组件而不脱离如由所附权利要求书定义的本发明的真实精神和范围。图示可能未必按比例绘制。归因于制造工艺的变化等等,本发明中的艺术再现与实际设备之间可能存在区别。可存在并未特定说明的本发明的其它实施例。应将本说明书及图式视为说明性的而非限制性的。可做出修改,以使具体情况、材料、物质组成、方法或工艺适应于本发明的目标、精神和范围。所有此类修改都既定在所附权利要求书的范围内。虽然本文揭示的方法已参考按特定次序执行的特定操作加以描述,但应理解,可在不脱离本发明的教示的情况下组合、细分或重新排序这些操作以形成等效方法。因此,除非本文中特别指示,否则操作的次序及分组并非对本发明的限制。
Claims (20)
1.一种半导体封装装置,其包括:
第一裸片,其具有第一表面和与所述第一表面相对的第二表面,所述第一裸片包括安置在所述第一裸片的所述第一表面处的第一电极和安置在所述第一裸片的所述第二表面处的第二电极;
粘合剂层,其安置于所述第一裸片的所述第一表面上;以及
囊封剂层,其囊封所述第一裸片和所述粘合剂层,其中所述第二电极的大体上整个表面从所述囊封剂层暴露。
2.根据权利要求1所述的半导体封装装置,其进一步包括安置于所述囊封剂层上的第一导电层,其中所述第一导电层与所述第二电极成热和电连通且覆盖所述第二电极的大体上所述整个表面。
3.根据权利要求2所述的半导体封装装置,其中所述囊封剂层的横向表面与所述第一导电层的侧表面大体上共面。
4.根据权利要求2所述的半导体封装装置,其进一步包括安置在所述囊封剂层中的电连接到所述第一导电层的第一导电通孔。
5.根据权利要求4所述的半导体封装装置,其进一步包括:
第二裸片,其安置在所述囊封剂层中;
第二粘合剂层,其安置于所述第二裸片上和所述囊封剂层中;
第二导电通孔,其安置在所述第二粘合剂层中且电连接到所述第二裸片;
第三导电通孔,其安置在所述囊封剂层中且电连接到所述第一导电层;
图案化导电层,其安置于所述囊封剂层上且电连接到所述第一导电通孔、所述第二导电通孔和所述第三导电通孔。
6.根据权利要求5所述的半导体封装装置,其进一步包括安置于所述第三导电通孔和所述囊封剂层之间的第一晶种层。
7.根据权利要求1所述的半导体封装装置,其进一步包括安置在所述粘合剂层中的第一导电通孔,其中所述第一电极的表面的至少一部分从所述粘合剂层暴露且电连接到所述第一导电通孔。
8.根据权利要求7所述的半导体封装装置,其进一步包括:
第一晶种层,其安置于所述第一电极和所述第一导电通孔之间以及所述第一导电通孔和所述粘合剂层之间。
9.根据权利要求1所述的半导体封装装置,其进一步包括:
第一导电通孔,其安置在所述第一粘合剂层中且电连接到所述第一裸片;
第二裸片,其安置在所述囊封剂层中;
第二粘合剂层,其安置于所述第二裸片上和所述囊封剂层中;
第二导电通孔,其安置在所述第二粘合剂层中且电连接到所述第二裸片;以及
图案化导电层,其安置于所述囊封剂层上且电连接到所述第一导电通孔和所述第二导电通孔。
10.根据权利要求9所述的半导体封装装置,其进一步包括安置于所述囊封剂层上且电连接到所述第二电极的第一导电层。
11.根据权利要求10所述的半导体封装装置,其进一步包括安置在所述囊封剂层中且电连接到所述第一导电层的第三导电通孔。
12.根据权利要求1所述的半导体封装装置,其进一步包括安置于所述第一裸片的所述第二表面上的第一导电层。
13.根据权利要求1所述的半导体封装装置,其进一步包括:
第一导电通孔,其安置在所述第一粘合剂层中且电连接到所述第一裸片;以及
图案化导电层,其安置于所述囊封剂层上且电连接到所述第一导电通孔。
14.一种制造半导体封装装置的方法,所述方法包括:
提供具有安置在其上的第一导电层的载体;
将第一裸片的第一侧经由第一粘合剂层附接到所述载体,所述第一裸片包括安置在所述第一侧的第一电极和安置在与所述第一侧相对的第二侧的第二电极;
用囊封剂囊封所述第一裸片和所述第一粘合剂层,使得所述第一裸片的所述第二电极的大体上整个表面从所述囊封剂暴露;以及
移除所述载体。
15.根据权利要求14所述的方法,其进一步包括移除所述第一导电层的一部分和所述第一粘合剂层的一部分从而形成暴露所述第一电极的开口。
16.根据权利要求15所述的方法,其进一步包括用导电材料填充所述开口从而形成第一导电通孔。
17.根据权利要求14所述的方法,其进一步包括在所述囊封剂上形成第二导电层,且将所述第二导电层电连接到所述第二电极。
18.根据权利要求17所述的方法,其进一步包括:
移除所述第一导电层的一部分和所述第一粘合剂层的一部分从而形成暴露所述第一电极的开口;以及
用导电材料填充所述开口从而形成第一导电通孔,
其中所述第一导电层和所述第一导电通孔的所述形成在单一操作中执行。
19.根据权利要求17所述的方法,其进一步包括:
移除所述第一导电层的一部分和所述第一粘合剂层的一部分从而形成暴露所述第一电极的开口;以及
用导电材料填充所述第一开口从而形成第一导电通孔;以及
在所述囊封剂中形成第二导电通孔。
20.根据权利要求14所述的方法,其进一步包括:
在邻近于其中所述第一裸片待放置在所述载体上的区域处形成导电立柱;
当囊封所述第一裸片和所述第一粘合剂层时囊封所述导电立柱;以及
暴露所述导电立柱。
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Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN109075151B (zh) | 2016-04-26 | 2023-06-27 | 亚德诺半导体国际无限责任公司 | 用于组件封装电路的机械配合、和电及热传导的引线框架 |
KR102561987B1 (ko) * | 2017-01-11 | 2023-07-31 | 삼성전기주식회사 | 반도체 패키지와 그 제조 방법 |
TWI614844B (zh) * | 2017-03-31 | 2018-02-11 | 矽品精密工業股份有限公司 | 封裝堆疊結構及其製法 |
WO2019066992A1 (en) * | 2017-09-30 | 2019-04-04 | Intel Corporation | HOUSING HAVING A HIGHLY CONDUCTIVE LAYER DEPOSITED ON AN ADDITIVE DEPOSIT CHIP BEFORE A TIM1 APPLICATION |
US10497635B2 (en) | 2018-03-27 | 2019-12-03 | Linear Technology Holding Llc | Stacked circuit package with molded base having laser drilled openings for upper package |
US11640968B2 (en) * | 2018-11-06 | 2023-05-02 | Texas Instruments Incorporated | Inductor on microelectronic die |
US11410977B2 (en) | 2018-11-13 | 2022-08-09 | Analog Devices International Unlimited Company | Electronic module for high power applications |
DE102019103281B4 (de) * | 2019-02-11 | 2023-03-16 | Infineon Technologies Ag | Verfahren zum bilden eines die-gehäuses |
KR20210027567A (ko) * | 2019-08-28 | 2021-03-11 | 삼성전자주식회사 | 반도체 패키지 |
CN110662352A (zh) * | 2019-10-28 | 2020-01-07 | 维沃移动通信有限公司 | 一种电路板装置及其加工方法和移动终端 |
CN212517170U (zh) * | 2020-05-30 | 2021-02-09 | 华为技术有限公司 | 一种芯片封装结构及电子设备 |
US11844178B2 (en) | 2020-06-02 | 2023-12-12 | Analog Devices International Unlimited Company | Electronic component |
Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050139985A1 (en) * | 2003-12-25 | 2005-06-30 | Norio Takahashi | Semiconductor chip package and multichip package |
US20070085182A1 (en) * | 2005-10-14 | 2007-04-19 | Tadashi Yamaguchi | Semiconductor device and fabrication method thereof |
CN101071810A (zh) * | 2006-05-12 | 2007-11-14 | 株式会社瑞萨科技 | 半导体器件 |
CN101334532A (zh) * | 2007-06-29 | 2008-12-31 | 康博丽贸易(上海)有限公司 | 偏光树脂光学镜片及其制造工艺 |
CN101342813A (zh) * | 2007-07-13 | 2009-01-14 | 施乐公司 | 用于阵列裸片放置的自对准精确基准 |
CN101369566A (zh) * | 2007-08-16 | 2009-02-18 | 海力士半导体有限公司 | 适于叠层半导体封装的半导体封装通过电极及半导体封装 |
CN104051392A (zh) * | 2013-03-15 | 2014-09-17 | 日月光半导体制造股份有限公司 | 半导体晶片、半导体工艺和半导体封装 |
CN105271104A (zh) * | 2014-06-06 | 2016-01-27 | 日月光半导体制造股份有限公司 | 半导体封装结构的制造方法 |
Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7759777B2 (en) | 2007-04-16 | 2010-07-20 | Infineon Technologies Ag | Semiconductor module |
US9318441B2 (en) * | 2007-12-14 | 2016-04-19 | Stats Chippac, Ltd. | Semiconductor device and method of forming sacrificial adhesive over contact pads of semiconductor die |
US8227908B2 (en) | 2008-07-07 | 2012-07-24 | Infineon Technologies Ag | Electronic device having contact elements with a specified cross section and manufacturing thereof |
US8003496B2 (en) * | 2009-08-14 | 2011-08-23 | Stats Chippac, Ltd. | Semiconductor device and method of mounting semiconductor die to heat spreader on temporary carrier and forming polymer layer and conductive layer over the die |
US8120158B2 (en) | 2009-11-10 | 2012-02-21 | Infineon Technologies Ag | Laminate electronic device |
US8435837B2 (en) * | 2009-12-15 | 2013-05-07 | Silicon Storage Technology, Inc. | Panel based lead frame packaging method and device |
US8421226B2 (en) * | 2010-02-25 | 2013-04-16 | Infineon Technologies Ag | Device including an encapsulated semiconductor chip and manufacturing method thereof |
US8294276B1 (en) * | 2010-05-27 | 2012-10-23 | Amkor Technology, Inc. | Semiconductor device and fabricating method thereof |
CN102157408B (zh) * | 2011-01-31 | 2012-11-21 | 江阴长电先进封装有限公司 | 通孔互联型圆片级mosfet封装结构及实现方法 |
US8685790B2 (en) * | 2012-02-15 | 2014-04-01 | Freescale Semiconductor, Inc. | Semiconductor device package having backside contact and method for manufacturing |
US9040346B2 (en) * | 2012-05-03 | 2015-05-26 | Infineon Technologies Ag | Semiconductor package and methods of formation thereof |
TWI473217B (zh) * | 2012-07-19 | 2015-02-11 | 矽品精密工業股份有限公司 | 半導體封裝件及其製法 |
US9111912B2 (en) * | 2013-05-30 | 2015-08-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3D packages and methods for forming the same |
US10032704B2 (en) * | 2015-02-13 | 2018-07-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Reducing cracking by adjusting opening size in pop packages |
CN109904127B (zh) * | 2015-06-16 | 2023-09-26 | 合肥矽迈微电子科技有限公司 | 封装结构及封装方法 |
US9899285B2 (en) * | 2015-07-30 | 2018-02-20 | Semtech Corporation | Semiconductor device and method of forming small Z semiconductor package |
-
2017
- 2017-07-13 US US15/649,545 patent/US10186467B2/en active Active
- 2017-07-13 US US15/649,543 patent/US10777478B2/en active Active
- 2017-07-14 CN CN201710574710.9A patent/CN107622989B/zh active Active
- 2017-07-14 CN CN201710575904.0A patent/CN107622983B/zh active Active
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050139985A1 (en) * | 2003-12-25 | 2005-06-30 | Norio Takahashi | Semiconductor chip package and multichip package |
US20070085182A1 (en) * | 2005-10-14 | 2007-04-19 | Tadashi Yamaguchi | Semiconductor device and fabrication method thereof |
CN101071810A (zh) * | 2006-05-12 | 2007-11-14 | 株式会社瑞萨科技 | 半导体器件 |
CN101334532A (zh) * | 2007-06-29 | 2008-12-31 | 康博丽贸易(上海)有限公司 | 偏光树脂光学镜片及其制造工艺 |
CN101342813A (zh) * | 2007-07-13 | 2009-01-14 | 施乐公司 | 用于阵列裸片放置的自对准精确基准 |
CN101369566A (zh) * | 2007-08-16 | 2009-02-18 | 海力士半导体有限公司 | 适于叠层半导体封装的半导体封装通过电极及半导体封装 |
CN104051392A (zh) * | 2013-03-15 | 2014-09-17 | 日月光半导体制造股份有限公司 | 半导体晶片、半导体工艺和半导体封装 |
CN105271104A (zh) * | 2014-06-06 | 2016-01-27 | 日月光半导体制造股份有限公司 | 半导体封装结构的制造方法 |
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US10777478B2 (en) | 2020-09-15 |
US10186467B2 (en) | 2019-01-22 |
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US20180019175A1 (en) | 2018-01-18 |
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