JP4936665B2 - 集積回路におけるコンタクトサイズをサイジングすることによって多層コンタクトを製造するための方法 - Google Patents

集積回路におけるコンタクトサイズをサイジングすることによって多層コンタクトを製造するための方法 Download PDF

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Publication number
JP4936665B2
JP4936665B2 JP2004526030A JP2004526030A JP4936665B2 JP 4936665 B2 JP4936665 B2 JP 4936665B2 JP 2004526030 A JP2004526030 A JP 2004526030A JP 2004526030 A JP2004526030 A JP 2004526030A JP 4936665 B2 JP4936665 B2 JP 4936665B2
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Prior art keywords
opening
etching
depth
contact
lag
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JP2005535124A (ja
JP2005535124A5 (https=
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ヘリッヒ ケイ
アムニプール マスード
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Advanced Micro Devices Inc
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Advanced Micro Devices Inc
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/089—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)
  • Electrodes Of Semiconductors (AREA)
JP2004526030A 2002-08-02 2003-07-09 集積回路におけるコンタクトサイズをサイジングすることによって多層コンタクトを製造するための方法 Expired - Lifetime JP4936665B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10/210,995 2002-08-02
US10/210,995 US6828240B2 (en) 2002-08-02 2002-08-02 Method of manufacturing multi-level contacts by sizing of contact sizes in integrated circuits
PCT/US2003/021282 WO2004013908A1 (en) 2002-08-02 2003-07-09 Method of manufacturing multi-level contacts by sizing of contact sizes in integrated circuits

Publications (3)

Publication Number Publication Date
JP2005535124A JP2005535124A (ja) 2005-11-17
JP2005535124A5 JP2005535124A5 (https=) 2012-03-08
JP4936665B2 true JP4936665B2 (ja) 2012-05-23

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JP2004526030A Expired - Lifetime JP4936665B2 (ja) 2002-08-02 2003-07-09 集積回路におけるコンタクトサイズをサイジングすることによって多層コンタクトを製造するための方法

Country Status (8)

Country Link
US (1) US6828240B2 (https=)
EP (1) EP1525612A1 (https=)
JP (1) JP4936665B2 (https=)
KR (1) KR100962312B1 (https=)
CN (1) CN100413050C (https=)
AU (1) AU2003256458A1 (https=)
TW (1) TWI308374B (https=)
WO (1) WO2004013908A1 (https=)

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US7470630B1 (en) * 2005-04-14 2008-12-30 Altera Corporation Approach to reduce parasitic capacitance from dummy fill
US7838203B1 (en) 2006-11-13 2010-11-23 National Semiconductor Corporation System and method for providing process compliant layout optimization using optical proximity correction to improve CMOS compatible non volatile memory retention reliability
US20080113483A1 (en) * 2006-11-15 2008-05-15 Micron Technology, Inc. Methods of etching a pattern layer to form staggered heights therein and intermediate semiconductor device structures
US7629255B2 (en) * 2007-06-04 2009-12-08 Lam Research Corporation Method for reducing microloading in etching high aspect ratio structures
US7855146B1 (en) 2007-09-18 2010-12-21 National Semiconductor Corporation Photo-focus modulation method for forming transistor gates and related transistor devices
US20090221144A1 (en) * 2008-03-03 2009-09-03 National Applied Research Laboratories Manufacturing method for nano scale Ge metal structure
US7790491B1 (en) 2008-05-07 2010-09-07 National Semiconductor Corporation Method for forming non-volatile memory cells and related apparatus and system
US7786017B1 (en) 2009-09-17 2010-08-31 International Business Machines Corporation Utilizing inverse reactive ion etching lag in double patterning contact formation
US9343463B2 (en) * 2009-09-29 2016-05-17 Headway Technologies, Inc. Method of high density memory fabrication
US8227339B2 (en) * 2009-11-02 2012-07-24 International Business Machines Corporation Creation of vias and trenches with different depths
US8736069B2 (en) 2012-08-23 2014-05-27 Macronix International Co., Ltd. Multi-level vertical plug formation with stop layers of increasing thicknesses
US8987914B2 (en) 2013-02-07 2015-03-24 Macronix International Co., Ltd. Conductor structure and method
US9214351B2 (en) 2013-03-12 2015-12-15 Macronix International Co., Ltd. Memory architecture of thin film 3D array
US8993429B2 (en) 2013-03-12 2015-03-31 Macronix International Co., Ltd. Interlayer conductor structure and method
US9117526B2 (en) 2013-07-08 2015-08-25 Macronix International Co., Ltd. Substrate connection of three dimensional NAND for improving erase performance
US9070447B2 (en) 2013-09-26 2015-06-30 Macronix International Co., Ltd. Contact structure and forming method
US8970040B1 (en) 2013-09-26 2015-03-03 Macronix International Co., Ltd. Contact structure and forming method
US9343322B2 (en) 2014-01-17 2016-05-17 Macronix International Co., Ltd. Three dimensional stacking memory film structure
US9559113B2 (en) 2014-05-01 2017-01-31 Macronix International Co., Ltd. SSL/GSL gate oxide in 3D vertical channel NAND
US9721964B2 (en) 2014-06-05 2017-08-01 Macronix International Co., Ltd. Low dielectric constant insulating material in 3D memory
US9356040B2 (en) 2014-06-27 2016-05-31 Macronix International Co., Ltd. Junction formation for vertical gate 3D NAND memory
TWI566365B (zh) * 2014-07-07 2017-01-11 旺宏電子股份有限公司 接觸結構及形成方法以及應用其之回路
US9379129B1 (en) 2015-04-13 2016-06-28 Macronix International Co., Ltd. Assist gate structures for three-dimensional (3D) vertical gate array memory structure
US9478259B1 (en) 2015-05-05 2016-10-25 Macronix International Co., Ltd. 3D voltage switching transistors for 3D vertical gate memory array
US9425209B1 (en) 2015-09-04 2016-08-23 Macronix International Co., Ltd. Multilayer 3-D structure with mirror image landing regions
US20170213885A1 (en) * 2016-01-21 2017-07-27 Micron Technology, Inc. Semiconductor structure and fabricating method thereof
US11031279B2 (en) * 2016-12-14 2021-06-08 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device with reduced trench loading effect
DE102018122473B4 (de) * 2017-09-29 2025-08-14 Taiwan Semiconductor Manufacturing Company, Ltd. Herstellungsverfahren für eine Halbleitervorrichtung
US10571758B2 (en) * 2018-01-05 2020-02-25 Innolux Corporation Display device
CN110970297B (zh) * 2018-09-29 2024-06-07 长鑫存储技术有限公司 补偿性蚀刻方法及结构、半导体器件及其制备方法
KR102783919B1 (ko) 2019-03-19 2025-03-24 삼성전자주식회사 반도체 소자
CN110767629B (zh) * 2019-10-30 2021-07-06 中国科学院微电子研究所 用于测量不同材料的蚀刻选择比的结构及方法
US11600628B2 (en) * 2020-01-15 2023-03-07 Globalfoundries U.S. Inc. Floating gate memory cell and memory array structure
WO2023028825A1 (zh) * 2021-08-31 2023-03-09 长江存储科技有限责任公司 一种半导体器件及其制备方法

Citations (3)

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Publication number Priority date Publication date Assignee Title
JPH05315457A (ja) * 1992-05-07 1993-11-26 Mitsubishi Electric Corp 半導体装置およびその製造方法
JPH08316320A (ja) * 1995-05-22 1996-11-29 Nec Corp 半導体装置の製造方法
JP2001044441A (ja) * 1999-07-29 2001-02-16 Sony Corp 完全空乏ｓｏｉ型半導体装置及び集積回路

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JPH05121369A (ja) 1991-10-24 1993-05-18 Oki Electric Ind Co Ltd 半導体装置のコンタクトホールエツチング方法
JPH05267251A (ja) * 1992-03-18 1993-10-15 Oki Electric Ind Co Ltd 半導体装置におけるコンタクトホールの形成方法
US5814547A (en) * 1997-10-06 1998-09-29 Industrial Technology Research Institute Forming different depth trenches simultaneously by microloading effect
KR100265596B1 (ko) * 1997-10-27 2000-10-02 김영환 반도체 소자의 제조방법
US5994780A (en) * 1997-12-16 1999-11-30 Advanced Micro Devices, Inc. Semiconductor device with multiple contact sizes
US6207534B1 (en) * 1999-09-03 2001-03-27 Chartered Semiconductor Manufacturing Ltd. Method to form narrow and wide shallow trench isolations with different trench depths to eliminate isolation oxide dishing
US6211059B1 (en) * 1999-10-29 2001-04-03 Nec Corporation Method of manufacturing semiconductor device having contacts with different depths
US6380087B1 (en) 2000-06-19 2002-04-30 Chartered Semiconductor Manufacturing Inc. CMP process utilizing dummy plugs in damascene process
DE10054109C2 (de) * 2000-10-31 2003-07-10 Advanced Micro Devices Inc Verfahren zum Bilden eines Substratkontakts in einem Feldeffekttransistor, der über einer vergrabenen Isolierschicht gebildet ist
US6294423B1 (en) * 2000-11-21 2001-09-25 Infineon Technologies North America Corp. Method for forming and filling isolation trenches
US6566191B2 (en) * 2000-12-05 2003-05-20 International Business Machines Corporation Forming electronic structures having dual dielectric thicknesses and the structure so formed

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05315457A (ja) * 1992-05-07 1993-11-26 Mitsubishi Electric Corp 半導体装置およびその製造方法
JPH08316320A (ja) * 1995-05-22 1996-11-29 Nec Corp 半導体装置の製造方法
JP2001044441A (ja) * 1999-07-29 2001-02-16 Sony Corp 完全空乏ｓｏｉ型半導体装置及び集積回路

Also Published As

Publication number Publication date
KR20050039840A (ko) 2005-04-29
AU2003256458A1 (en) 2004-02-23
CN100413050C (zh) 2008-08-20
TW200402832A (en) 2004-02-16
TWI308374B (en) 2009-04-01
US20040023499A1 (en) 2004-02-05
KR100962312B1 (ko) 2010-06-10
US6828240B2 (en) 2004-12-07
WO2004013908A1 (en) 2004-02-12
CN1672256A (zh) 2005-09-21
EP1525612A1 (en) 2005-04-27
JP2005535124A (ja) 2005-11-17

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