JP4797185B2 - 縦型リプレイスメント・ゲート・トランジスタと両立性のあるバイポーラ接合トランジスタ - Google Patents

縦型リプレイスメント・ゲート・トランジスタと両立性のあるバイポーラ接合トランジスタ Download PDF

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JP4797185B2
JP4797185B2 JP2002270858A JP2002270858A JP4797185B2 JP 4797185 B2 JP4797185 B2 JP 4797185B2 JP 2002270858 A JP2002270858 A JP 2002270858A JP 2002270858 A JP2002270858 A JP 2002270858A JP 4797185 B2 JP4797185 B2 JP 4797185B2
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doped
region
insulating layer
forming
layer
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JP2002270858A
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Japanese (ja)
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JP2003179067A5 (enExample
JP2003179067A (ja
Inventor
チャードリィ サミア
アーサー レイマン ポール
ルッセル マックマッケン ジョン
トムソン ロス
キングシェング ザオ ジャック
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Agere Systems LLC
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Agere Systems LLC
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D10/00—Bipolar junction transistors [BJT]
    • H10D10/01—Manufacture or treatment
    • H10D10/051—Manufacture or treatment of vertical BJTs
    • H10D10/054—Forming extrinsic base regions on silicon substrate after insulating device isolation in vertical BJTs having single crystalline emitter, collector or base regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/025—Manufacture or treatment of FETs having insulated gates [IGFET] of vertical IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/63—Vertical IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/017—Manufacture or treatment using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0107—Integrating at least one component covered by H10D12/00 or H10D30/00 with at least one component covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating IGFETs with BJTs
    • H10D84/0109—Integrating at least one component covered by H10D12/00 or H10D30/00 with at least one component covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating IGFETs with BJTs the at least one component covered by H10D12/00 or H10D30/00 being a MOS device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0112—Integrating together multiple components covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating multiple BJTs
    • H10D84/0119—Integrating together multiple components covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating multiple BJTs the components including complementary BJTs
    • H10D84/0121—Integrating together multiple components covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating multiple BJTs the components including complementary BJTs the complementary BJTs being vertical BJTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D10/00—Bipolar junction transistors [BJT]
    • H10D10/40—Vertical BJTs

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  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Bipolar Transistors (AREA)
  • Bipolar Integrated Circuits (AREA)
JP2002270858A 2001-09-18 2002-09-18 縦型リプレイスメント・ゲート・トランジスタと両立性のあるバイポーラ接合トランジスタ Expired - Fee Related JP4797185B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/956,382 US6759730B2 (en) 2001-09-18 2001-09-18 Bipolar junction transistor compatible with vertical replacement gate transistor
US09/956382 2001-09-18

Publications (3)

Publication Number Publication Date
JP2003179067A JP2003179067A (ja) 2003-06-27
JP2003179067A5 JP2003179067A5 (enExample) 2005-11-04
JP4797185B2 true JP4797185B2 (ja) 2011-10-19

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JP2002270858A Expired - Fee Related JP4797185B2 (ja) 2001-09-18 2002-09-18 縦型リプレイスメント・ゲート・トランジスタと両立性のあるバイポーラ接合トランジスタ

Country Status (5)

Country Link
US (1) US6759730B2 (enExample)
JP (1) JP4797185B2 (enExample)
KR (1) KR100918779B1 (enExample)
GB (1) GB2383190B (enExample)
TW (1) TW569451B (enExample)

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US9209095B2 (en) 2014-04-04 2015-12-08 International Business Machines Corporation III-V, Ge, or SiGe fin base lateral bipolar transistor structure and method

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KR20180066708A (ko) * 2016-12-09 2018-06-19 삼성전자주식회사 반도체 장치 및 그 제조 방법
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US10269800B2 (en) * 2017-05-26 2019-04-23 Taiwan Semiconductor Manufacturing Co., Ltd. Vertical gate semiconductor device with steep subthreshold slope
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JP7056994B2 (ja) * 2018-05-08 2022-04-19 ユニサンティス エレクトロニクス シンガポール プライベート リミテッド 柱状半導体装置の製造方法
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Publication number Priority date Publication date Assignee Title
US9209095B2 (en) 2014-04-04 2015-12-08 International Business Machines Corporation III-V, Ge, or SiGe fin base lateral bipolar transistor structure and method

Also Published As

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KR20030024626A (ko) 2003-03-26
GB0220210D0 (en) 2002-10-09
GB2383190B (en) 2006-05-24
GB2383190A (en) 2003-06-18
TW569451B (en) 2004-01-01
US20030052721A1 (en) 2003-03-20
JP2003179067A (ja) 2003-06-27
KR100918779B1 (ko) 2009-09-23
US6759730B2 (en) 2004-07-06

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