JP4764160B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP4764160B2 JP4764160B2 JP2005368161A JP2005368161A JP4764160B2 JP 4764160 B2 JP4764160 B2 JP 4764160B2 JP 2005368161 A JP2005368161 A JP 2005368161A JP 2005368161 A JP2005368161 A JP 2005368161A JP 4764160 B2 JP4764160 B2 JP 4764160B2
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- 239000004065 semiconductor Substances 0.000 title claims description 51
- 238000002955 isolation Methods 0.000 claims description 33
- 239000000758 substrate Substances 0.000 claims description 13
- 238000004519 manufacturing process Methods 0.000 description 40
- 238000005530 etching Methods 0.000 description 24
- 238000000034 method Methods 0.000 description 10
- 230000000694 effects Effects 0.000 description 9
- 239000011248 coating agent Substances 0.000 description 7
- 238000000576 coating method Methods 0.000 description 7
- 239000000463 material Substances 0.000 description 7
- 238000010586 diagram Methods 0.000 description 6
- 238000001459 lithography Methods 0.000 description 6
- 238000001312 dry etching Methods 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 4
- 238000000059 patterning Methods 0.000 description 4
- 238000000231 atomic layer deposition Methods 0.000 description 3
- 239000000470 constituent Substances 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000009977 dual effect Effects 0.000 description 2
- 239000005368 silicate glass Substances 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910005883 NiSi Inorganic materials 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823864—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823871—Complementary field-effect transistors, e.g. CMOS interconnection or wiring or contact manufacturing related aspects
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7843—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being an applied insulating layer
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Element Separation (AREA)
Description
第1の実施形態は、CMOS回路を構成するnMOSFETとpMOSFETの境界領域においてコンタクトエッチングストッパ膜(以下、ストッパ膜と称す)を重ねつつ、ゲート電極上のコンタクト開孔と素子領域上のコンタクト開孔によるエッチング時間が同等となるように境界領域のゲート電極上のストッパ膜の膜厚を薄くする例である。
第2の実施形態は、第1の実施形態におけるNSG膜17を塗布膜に変更した例である。尚、以下の説明で省略した部分については第1の実施形態と同様である。
第3の実施形態は、第1の実施形態の製造方法におけるNSG膜17及びストッパ膜16の平坦化工程をCMPとドライエッチングの2種類の手法で行う例である。尚、以下の説明で省略した部分については第1の実施形態と同様である。
第4の実施形態は、ゲート電極に接続するコンタクトC1をnMOSFET及びpMOSFET間の境界領域以外のストッパ膜15,16の重ならない領域に配置する例である。
第5の実施形態は、第4の実施形態と同様、ゲート電極に接続するコンタクトをnMOSFET及びpMOSFET間の境界領域以外に配置する例である。さらに、第5の実施形態では、境界領域からゲート電極を引き出してコンタクトのための領域を設けている。
第6の実施形態は、ゲート電極13がマルチフィンガー(Multi-Finger)タイプの例である。
Claims (2)
- 半導体基板と、
前記半導体基板内に設けられた第1の素子領域と、
前記第1の素子領域と離間し、前記半導体基板内に設けられた第2の素子領域と、
前記第1及び第2の素子領域間の前記半導体基板内に設けられた素子分離絶縁膜と、
前記素子分離絶縁膜、前記第1及び第2の素子領域を跨いで延在されたゲート電極と、
前記ゲート電極及び前記第1の素子領域上に形成され、前記第1の素子領域を覆い、引っ張り応力を与える第1のストッパ膜と、
前記ゲート電極及び前記第2の素子領域上に形成され、前記第2の素子領域を覆い、圧縮応力を与える第2のストッパ膜と、
前記素子分離絶縁膜上において前記ゲート電極に接続されたコンタクトと
を具備し、
前記素子分離絶縁膜上において前記第1及び第2のストッパ膜の少なくとも一部が重なり、
前記素子分離絶縁膜上における前記第1及び第2のストッパ膜の合計膜厚であって、前記ゲート電極上の合計膜厚は前記ゲート電極上以外の合計膜厚より薄い
ことを特徴とする半導体装置。 - 前記素子分離絶縁膜上において重なった前記第1及び第2のストッパ膜のうち上層のストッパ膜は、前記素子分離絶縁膜上における前記ゲート電極上には存在しないことを特徴とする請求項1に記載の半導体装置。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005368161A JP4764160B2 (ja) | 2005-12-21 | 2005-12-21 | 半導体装置 |
US11/635,761 US7427544B2 (en) | 2005-12-21 | 2006-12-08 | Semiconductor device and method of manufacturing the same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005368161A JP4764160B2 (ja) | 2005-12-21 | 2005-12-21 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2007173466A JP2007173466A (ja) | 2007-07-05 |
JP4764160B2 true JP4764160B2 (ja) | 2011-08-31 |
Family
ID=38192631
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2005368161A Expired - Fee Related JP4764160B2 (ja) | 2005-12-21 | 2005-12-21 | 半導体装置 |
Country Status (2)
Country | Link |
---|---|
US (1) | US7427544B2 (ja) |
JP (1) | JP4764160B2 (ja) |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4899085B2 (ja) * | 2006-03-03 | 2012-03-21 | 富士通セミコンダクター株式会社 | 半導体装置およびその製造方法 |
US7638837B2 (en) * | 2007-09-25 | 2009-12-29 | Globalfoundries Inc. | Stress enhanced semiconductor device and methods for fabricating same |
US20090215277A1 (en) * | 2008-02-26 | 2009-08-27 | Tung-Hsing Lee | Dual contact etch stop layer process |
JP5262370B2 (ja) | 2008-07-10 | 2013-08-14 | 富士通セミコンダクター株式会社 | 半導体装置の製造方法、及び半導体装置 |
FR3007198B1 (fr) | 2013-06-13 | 2015-06-19 | St Microelectronics Rousset | Composant, par exemple transistor nmos, a region active a contraintes en compression relachees, et procede de fabrication |
FR3007196A1 (fr) * | 2013-06-13 | 2014-12-19 | St Microelectronics Rousset | Transistor nmos a region active a contraintes en compression relachees |
FR3007195A1 (fr) * | 2013-06-13 | 2014-12-19 | St Microelectronics Rousset | Transistor nmos a region active a contraintes en compression relachees, et procede de fabrication |
FR3018139B1 (fr) | 2014-02-28 | 2018-04-27 | Stmicroelectronics (Rousset) Sas | Circuit integre a composants, par exemple transistors nmos, a regions actives a contraintes en compression relachees |
FR3025335B1 (fr) | 2014-08-29 | 2016-09-23 | Stmicroelectronics Rousset | Procede de fabrication d'un circuit integre rendant plus difficile une retro-conception du circuit integre et circuit integre correspondant |
JP6289652B2 (ja) | 2014-09-25 | 2018-03-07 | 合同会社パッチドコニックス | 流体を加圧し供給する装置、システム、および方法。 |
Family Cites Families (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH1079505A (ja) * | 1996-09-05 | 1998-03-24 | Hitachi Ltd | 半導体集積回路装置の製造方法 |
US6346438B1 (en) * | 1997-06-30 | 2002-02-12 | Kabushiki Kaisha Toshiba | Method of manufacturing a semiconductor device |
KR100247933B1 (ko) * | 1997-08-22 | 2000-03-15 | 윤종용 | 버티드 콘택을 갖는 반도체 소자 및 그 제조방법 |
TW434907B (en) * | 1998-12-09 | 2001-05-16 | Matsushita Electronics Corp | Semiconductor memory apparatus and its manufacturing method |
JP2001148472A (ja) * | 1999-09-07 | 2001-05-29 | Nec Corp | 半導体装置及びその製造方法 |
JP2002033484A (ja) * | 2000-07-18 | 2002-01-31 | Mitsubishi Electric Corp | 半導体装置 |
JP4313941B2 (ja) * | 2000-09-29 | 2009-08-12 | 株式会社東芝 | 半導体記憶装置 |
JP2003086708A (ja) * | 2000-12-08 | 2003-03-20 | Hitachi Ltd | 半導体装置及びその製造方法 |
JP2002198368A (ja) | 2000-12-26 | 2002-07-12 | Nec Corp | 半導体装置の製造方法 |
JP4037711B2 (ja) * | 2002-07-26 | 2008-01-23 | 株式会社東芝 | 層間絶縁膜内に形成されたキャパシタを有する半導体装置 |
JP4030383B2 (ja) * | 2002-08-26 | 2008-01-09 | 株式会社ルネサステクノロジ | 半導体装置およびその製造方法 |
JP4557508B2 (ja) * | 2003-06-16 | 2010-10-06 | パナソニック株式会社 | 半導体装置 |
JP2005322730A (ja) * | 2004-05-07 | 2005-11-17 | Renesas Technology Corp | 半導体装置及びその製造方法 |
JP2006339398A (ja) * | 2005-06-02 | 2006-12-14 | Sony Corp | 半導体装置の製造方法 |
US7514752B2 (en) * | 2005-08-26 | 2009-04-07 | Toshiba America Electronic Components, Inc. | Reduction of short-circuiting between contacts at or near a tensile-compressive boundary |
JP4765598B2 (ja) * | 2005-12-08 | 2011-09-07 | ソニー株式会社 | 半導体装置の製造方法 |
US7511360B2 (en) * | 2005-12-14 | 2009-03-31 | Freescale Semiconductor, Inc. | Semiconductor device having stressors and method for forming |
-
2005
- 2005-12-21 JP JP2005368161A patent/JP4764160B2/ja not_active Expired - Fee Related
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2006
- 2006-12-08 US US11/635,761 patent/US7427544B2/en active Active
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US20070145522A1 (en) | 2007-06-28 |
US7427544B2 (en) | 2008-09-23 |
JP2007173466A (ja) | 2007-07-05 |
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