JP2008218899A - 半導体装置及びその製造方法 - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 76
- 238000004519 manufacturing process Methods 0.000 title abstract description 51
- 238000002955 isolation Methods 0.000 claims description 49
- 239000000758 substrate Substances 0.000 claims description 48
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 28
- 229910052710 silicon Inorganic materials 0.000 claims description 28
- 239000010703 silicon Substances 0.000 claims description 28
- 239000012535 impurity Substances 0.000 claims description 10
- 238000000638 solvent extraction Methods 0.000 claims description 2
- 230000006835 compression Effects 0.000 abstract description 7
- 238000007906 compression Methods 0.000 abstract description 7
- 238000000034 method Methods 0.000 description 36
- 239000010410 layer Substances 0.000 description 33
- 230000000694 effects Effects 0.000 description 14
- 239000011229 interlayer Substances 0.000 description 13
- 229910021332 silicide Inorganic materials 0.000 description 12
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 12
- 239000002184 metal Substances 0.000 description 5
- 239000007772 electrode material Substances 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 230000001681 protective effect Effects 0.000 description 4
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 3
- 239000000470 constituent Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 230000009977 dual effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
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Abstract
【解決手段】FETにおけるソース/ドレイン領域14,15のコンタクト部19S,20S,19D,20Dが存在しない部分に、それぞれ埋め込み絶縁膜21S−1,21S−2,21S−3,21D−1,21D−2,21D−3を設けた。上記埋め込み酸化膜の体積膨張により発生する圧縮方向のストレスをFETのチャネル領域に印加することでホールの移動度を向上させ、ドレイン電流を増大させて性能を向上させる。
【選択図】 図1
Description
IEDM 2004 "Dual Stress Liner for High Performance sub-45nm Gate Length SOI CMOS Manufacturing" H.S.Yang et al. pp.1075-1078. IEDM 2003 "A 90nm High Volume Manufacturing Logic Technology Featuring Novel 45nm Gate Length Strained Silicon CMOS Transistor" T.Ghani et al. pp.978-980.
[第1の実施形態]
図1(a)〜(d)はそれぞれ、この発明の第1の実施形態に係る半導体装置について説明するためのものでPチャネル型MOSFETを示している。(a)図はパターン平面図、(b)図は(a)図のA−A’線に沿った断面図、(c)図は(a)図のB−B’線に沿った断面図、(d)図は(a)図のC−C’線に沿った断面図である。
図2(a)〜(c)はそれぞれ、この発明の第2の実施形態に係る半導体装置について説明するためのものでPチャネル型MOSFETを示している。(a)図はパターン平面図、(b)図は(a)図のD−D’線に沿った断面図、(c)図は(a)図のE−E’線に沿った断面図である。
図3は、この発明の第3の実施形態に係る半導体装置について説明するためのもので、Pチャネル型MOSFETのパターン平面図である。このFETでは、素子領域上に2本のゲート電極(図3ではシリサイド層16Ga,16Gbで示す)が配置されており、2つのFETでソース/ドレイン領域の一方(ここではドレイン領域)を共用している。また、コンタクト部19Sa,19D,19Sbは、ソース/ドレイン領域の一端側と他端側に交互に配置されている。更に、埋め込み酸化膜21Sa−1,21Sa−2はコンタクト部19Saを挟むように配置されており、埋め込み酸化膜21D−1,21D−2はコンタクト部19Dを挟むように配置されており、埋め込み酸化膜21Sb−1,21Sb−2はコンタクト部19Sbを挟むように配置されている。上記埋め込み酸化膜21Sa−1,21Sa−2,21D−1,21D−2,21Sb−1,21Sb−2の一端はそれぞれ、素子分離領域11に接している。
図4(a)〜(c)はそれぞれ、この発明の第4の実施形態に係る半導体装置について説明するためのものでPチャネル型MOSFETを示している。(a)図はパターン平面図、(b)図は(a)図のF−F’線に沿った断面図、(c)図は(a)図のC−C’線に沿った断面図である。
図5(a),(b)はそれぞれ、この発明の第5の実施形態に係る半導体装置について説明するための断面図である。上述した第1乃至第4の実施形態では、図5(a)に示すように埋め込み酸化膜21S,21Dがソース/ドレイン領域14,15の接合深さより浅い場合を例にとって説明した。
図6(a),(b)はそれぞれ、この発明の第6の実施形態に係る半導体装置について説明するための断面図である。図6(a),(b)は、SOIウェーハ(SOI基板)にPチャネル型MOSFETを形成した例を示している。SOI基板23には、半導体基板10上にBOX層24が形成され、このBOX層24上にシリコン層が形成されている。上記シリコン層23には、上記BOX層24に達する深さまで素子分離領域11が形成され、素子領域となる島状のシリコン領域25が形成されている。
図7(a),(b)乃至図11(a),(b)はそれぞれ、この発明の第7の実施形態に係る半導体装置の製造方法について説明するためのもので、図1(a)〜(d)に示したPチャネル型MOSFETの製造工程の一部を順次示している。(a)図はパターン平面図であり、(b)図は(a)図のG−G’線に沿った断面図である。
図12(a),(b)乃至図16(a),(b)はそれぞれ、この発明の第8の実施形態に係る半導体装置の製造方法について説明するためのもので、Pチャネル型MOSFETの製造工程の一部を順次示している。(a)図はパターン平面図であり、(b)図は(a)図のH−H’線に沿った断面図である。
図17(a),(b)乃至図21(a),(b)はそれぞれ、この発明の第9の実施形態に係る半導体装置の製造方法について説明するためのもので、図1(a)〜(d)に示したPチャネル型MOSFETの製造工程の一部を順次示している。(a)図はパターン平面図であり、(b)図は(a)図のI−I’線に沿った断面図である。
図22(a),(b)乃至図26(a),(b)はそれぞれ、この発明の第10の実施形態に係る半導体装置の製造方法について説明するためのもので、図1(a)〜(d)に示したPチャネル型MOSFETの製造工程の一部を順次示している。(a)図はパターン平面図であり、(b)図は(a)図のJ−J’線に沿った断面図である。
Claims (5)
- 半導体基板の主表面に形成された素子分離領域と、
前記素子分離領域で区画された素子領域の前記半導体基板上に、ゲート絶縁膜を介在して設けられたゲート電極と、
前記素子領域の前記半導体基板中に、前記ゲート電極を挟んで形成されたソース/ドレイン領域と、
前記ソース/ドレイン領域上にそれぞれ接続されたコンタクト部と、
前記ソース/ドレイン領域にそれぞれ埋め込み形成され、前記ソース/ドレイン領域間のチャネル領域に応力を与える埋め込み絶縁膜と
を具備することを特徴とする半導体装置。 - SOI基板のシリコン領域に形成された素子分離領域と、
前記素子分離領域で区画された島状のシリコン領域上に、ゲート絶縁膜を介在して形成されたゲート電極と、
前記島状のシリコン領域中に、前記ゲート電極を挟んで形成されたソース/ドレイン領域と、
前記ソース/ドレイン領域上にそれぞれ接続されたコンタクト部と、
前記ソース/ドレイン領域にそれぞれ埋め込み形成され、前記ソース/ドレイン領域間のチャネル領域に応力を与える埋め込み絶縁膜と
を具備することを特徴とする半導体装置。 - 前記埋め込み絶縁膜は、体積膨張によって前記ソース/ドレイン領域間のチャネル領域に圧縮応力を与える酸化膜であることを特徴とする請求項1または2に記載の半導体装置。
- 半導体基板の主表面に素子分離領域を形成する工程と、
前記素子分離領域で区画された素子領域上に、ゲート絶縁膜及びゲート電極を形成する工程と、
前記ゲート電極をマスクの一部に用いて前記素子領域中に不純物を導入し、ソース/ドレイン領域を形成する工程と、
前記ソース/ドレイン領域中にそれぞれ、体積膨張によりチャネル領域に圧縮応力を与える埋め込み絶縁膜を形成する工程と
を具備することを特徴とする半導体装置の製造方法。 - SOI基板のシリコン領域に素子分離領域を形成して区画し、島状のシリコン領域を形成する工程と、
島状のシリコン領域上に、ゲート絶縁膜及びゲート電極を形成する工程と、
前記島状のシリコン領域に前記ゲート電極をマスクの一部に用いて不純物を導入し、ソース/ドレイン領域を形成する工程と、
前記ソース/ドレイン領域中にそれぞれ、体積膨張によりチャネル領域に圧縮応力を与える埋め込み絶縁膜を形成する工程と
を具備することを特徴とする半導体装置の製造方法。
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JP2007057429A JP2008218899A (ja) | 2007-03-07 | 2007-03-07 | 半導体装置及びその製造方法 |
US12/043,453 US20080251842A1 (en) | 2007-03-07 | 2008-03-07 | P-Channel FET Whose Hole Mobility is Improved by Applying Stress to the Channel Region and a Method of Manufacturing the Same |
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