JP4753960B2 - 半導体モジュール、半導体モジュールの製造方法 - Google Patents

半導体モジュール、半導体モジュールの製造方法 Download PDF

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Publication number
JP4753960B2
JP4753960B2 JP2008091644A JP2008091644A JP4753960B2 JP 4753960 B2 JP4753960 B2 JP 4753960B2 JP 2008091644 A JP2008091644 A JP 2008091644A JP 2008091644 A JP2008091644 A JP 2008091644A JP 4753960 B2 JP4753960 B2 JP 4753960B2
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JP
Japan
Prior art keywords
insulating resin
resin layer
semiconductor
electrode
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2008091644A
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English (en)
Japanese (ja)
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JP2009246174A (ja
JP2009246174A5 (enExample
Inventor
良輔 臼井
恭典 井上
真弓 中里
克実 伊藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
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Sanyo Electric Co Ltd
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Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP2008091644A priority Critical patent/JP4753960B2/ja
Priority to CN2009801172074A priority patent/CN102027591B/zh
Priority to US12/935,854 priority patent/US8476776B2/en
Priority to PCT/JP2009/055307 priority patent/WO2009122911A1/ja
Publication of JP2009246174A publication Critical patent/JP2009246174A/ja
Publication of JP2009246174A5 publication Critical patent/JP2009246174A5/ja
Application granted granted Critical
Publication of JP4753960B2 publication Critical patent/JP4753960B2/ja
Expired - Fee Related legal-status Critical Current
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    • H10W74/111—
    • H10P72/74—
    • H10W70/09—
    • H10W74/014—
    • H10W74/019—
    • H10W74/129—
    • H10P72/742—
    • H10W70/60—
    • H10W70/655—
    • H10W72/01936—
    • H10W72/01951—
    • H10W72/01953—
    • H10W72/0198—
    • H10W72/241—
    • H10W72/242—
    • H10W72/244—
    • H10W72/29—
    • H10W72/922—
    • H10W72/9413—
    • H10W72/952—
    • H10W74/00—
    • H10W74/121—

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
JP2008091644A 2008-03-31 2008-03-31 半導体モジュール、半導体モジュールの製造方法 Expired - Fee Related JP4753960B2 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2008091644A JP4753960B2 (ja) 2008-03-31 2008-03-31 半導体モジュール、半導体モジュールの製造方法
CN2009801172074A CN102027591B (zh) 2008-03-31 2009-03-18 半导体模块、半导体模块的制造方法及便携式设备
US12/935,854 US8476776B2 (en) 2008-03-31 2009-03-18 Semiconductor module, method for fabricating the semiconductor module, and mobile apparatus
PCT/JP2009/055307 WO2009122911A1 (ja) 2008-03-31 2009-03-18 半導体モジュール、半導体モジュールの製造方法、ならびに携帯機器

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2008091644A JP4753960B2 (ja) 2008-03-31 2008-03-31 半導体モジュール、半導体モジュールの製造方法

Publications (3)

Publication Number Publication Date
JP2009246174A JP2009246174A (ja) 2009-10-22
JP2009246174A5 JP2009246174A5 (enExample) 2011-05-12
JP4753960B2 true JP4753960B2 (ja) 2011-08-24

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Family Applications (1)

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JP2008091644A Expired - Fee Related JP4753960B2 (ja) 2008-03-31 2008-03-31 半導体モジュール、半導体モジュールの製造方法

Country Status (4)

Country Link
US (1) US8476776B2 (enExample)
JP (1) JP4753960B2 (enExample)
CN (1) CN102027591B (enExample)
WO (1) WO2009122911A1 (enExample)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011077108A (ja) * 2009-09-29 2011-04-14 Elpida Memory Inc 半導体装置
JP5496692B2 (ja) 2010-01-22 2014-05-21 三洋電機株式会社 半導体モジュールの製造方法
KR101678052B1 (ko) * 2010-02-25 2016-11-22 삼성전자 주식회사 단층 배선 패턴을 포함한 인쇄회로기판(ｐｃｂ), ｐｃｂ를 포함한 반도체 패키지, 반도체 패키지를 포함한 전기전자장치, ｐｃｂ제조방법, 및 반도체 패키지 제조방법
US9748154B1 (en) 2010-11-04 2017-08-29 Amkor Technology, Inc. Wafer level fan out semiconductor device and manufacturing method thereof
JP5819999B2 (ja) * 2014-02-05 2015-11-24 ラピスセミコンダクタ株式会社 半導体装置およびその半導体装置の製造方法
CN105097758B (zh) 2014-05-05 2018-10-26 日月光半导体制造股份有限公司 衬底、其半导体封装及其制造方法
JPWO2023042450A1 (enExample) * 2021-09-14 2023-03-23

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08236586A (ja) * 1994-12-29 1996-09-13 Nitto Denko Corp 半導体装置及びその製造方法
EP1335422B1 (en) * 1995-03-24 2013-01-16 Shinko Electric Industries Co., Ltd. Process for making a chip sized semiconductor device
JPH08306828A (ja) * 1995-05-11 1996-11-22 Nitto Denko Corp 半導体装置
US6181569B1 (en) * 1999-06-07 2001-01-30 Kishore K. Chakravorty Low cost chip size package and method of fabricating the same
JP2001176898A (ja) * 1999-12-20 2001-06-29 Mitsui High Tec Inc 半導体パッケージの製造方法
JP2002083904A (ja) * 2000-09-06 2002-03-22 Sanyo Electric Co Ltd 半導体装置およびその製造方法
JP3923368B2 (ja) * 2002-05-22 2007-05-30 シャープ株式会社 半導体素子の製造方法
US6998532B2 (en) * 2002-12-24 2006-02-14 Matsushita Electric Industrial Co., Ltd. Electronic component-built-in module
JP2004349361A (ja) 2003-05-21 2004-12-09 Casio Comput Co Ltd 半導体装置およびその製造方法
JP4479209B2 (ja) * 2003-10-10 2010-06-09 パナソニック株式会社 電子回路装置およびその製造方法並びに電子回路装置の製造装置
WO2006093191A1 (ja) * 2005-03-01 2006-09-08 Nec Corporation 半導体パッケージ及びその製造方法
JP4428337B2 (ja) * 2005-12-02 2010-03-10 ソニー株式会社 半導体装置の製造方法
JP4877626B2 (ja) * 2006-02-16 2012-02-15 株式会社テラミクロス 半導体装置の製造方法
JP2008053693A (ja) * 2006-07-28 2008-03-06 Sanyo Electric Co Ltd 半導体モジュール、携帯機器、および半導体モジュールの製造方法

Also Published As

Publication number Publication date
JP2009246174A (ja) 2009-10-22
US20110193222A1 (en) 2011-08-11
CN102027591A (zh) 2011-04-20
US8476776B2 (en) 2013-07-02
WO2009122911A1 (ja) 2009-10-08
CN102027591B (zh) 2013-02-20

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