JP4744924B2 - Lsi内部信号観測回路 - Google Patents
Lsi内部信号観測回路 Download PDFInfo
- Publication number
- JP4744924B2 JP4744924B2 JP2005137391A JP2005137391A JP4744924B2 JP 4744924 B2 JP4744924 B2 JP 4744924B2 JP 2005137391 A JP2005137391 A JP 2005137391A JP 2005137391 A JP2005137391 A JP 2005137391A JP 4744924 B2 JP4744924 B2 JP 4744924B2
- Authority
- JP
- Japan
- Prior art keywords
- output
- lsi
- signal
- buffer
- monitor line
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2884—Testing of integrated circuits [IC] using dedicated test connectors, test elements or test circuits on the IC under test
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2855—Environmental, reliability or burn-in testing
- G01R31/2856—Internal circuit aspects, e.g. built-in test features; Test chips; Measuring material aspects, e.g. electro migration [EM]
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2853—Electrical testing of internal connections or -isolation, e.g. latch-up or chip-to-lead connections
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Description
2 モニタ線
31、32、3n バッファ
4 シールド線
E1、E2、En イネーブル信号
S1、S21、S22、Sn 出力信号線
C1、C21、C22、Cn キャパシタ
Claims (5)
- パッドと、
前記パッドに接続されてLSIの内部に配線されるモニタ線と、
前記モニタ線に隣接して配線され、電位が固定されているシールド線と、
出力イネーブル端子を有し前記LSIの内部ノードに接続されるバッファと、
前記バッファの出力と前記モニタ線との間に接続されるキャパシタと
を備え、
前記イネーブル端子に入力する出力イネーブル信号を制御して前記バッファを出力イネーブル状態にし、前記内部ノードの信号の変化を前記キャパシタを介して前記モニタ線に重畳して前記パッドで観測することを特徴とするLSI内部信号観測回路。 - パッドと、
前記パッドに接続されてLSIの内部に配線されるモニタ線と、
前記モニタ線に隣接して接続され、電位が固定されているシールド線と、
出力イネーブル端子を有し前記LSIの内部回路の複数のノードのそれぞれに接続される複数のバッファと、
前記複数のバッファのそれぞれの出力端子と前記モニタ線との間にそれぞれ接続される複数のキャパシタと
を備え、
前記複数のバッファのそれぞれの出力イネーブル端子に入力するそれぞれのイネーブル信号を制御して前記複数のバッファのいずれか1つを出力イネーブル状態にし、前記複数内部ノードのうちの所望のノードの信号の変化を前記出力イネーブル状態のバッファに接続された前記キャパシタを介して前記モニタ線に重畳して前記パッドで観測することを特徴とするLSI内部信号観測回路。 - 前記キャパシタが、前記モニタ線とこのモニタ線に隣接して引き回す前記バッファの出力信号線との間の配線間容量であることを特徴とする請求項1または2に記載のLSI内部信号観測回路。
- 前記バッファが、単極性出力型であることを特徴とする請求項1乃至3のいずれか1項に記載のLSI内部信号観測回路。
- 前記バッファが、双極性出力型であり、出力が相乗されて出力されることを特徴とする請求項1乃至3のいずれか1項に記載のLSI内部信号観測回路。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005137391A JP4744924B2 (ja) | 2005-05-10 | 2005-05-10 | Lsi内部信号観測回路 |
US11/415,584 US7805646B2 (en) | 2005-05-10 | 2006-05-01 | LSI internal signal observing circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005137391A JP4744924B2 (ja) | 2005-05-10 | 2005-05-10 | Lsi内部信号観測回路 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2006317170A JP2006317170A (ja) | 2006-11-24 |
JP4744924B2 true JP4744924B2 (ja) | 2011-08-10 |
Family
ID=37418454
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2005137391A Expired - Fee Related JP4744924B2 (ja) | 2005-05-10 | 2005-05-10 | Lsi内部信号観測回路 |
Country Status (2)
Country | Link |
---|---|
US (1) | US7805646B2 (ja) |
JP (1) | JP4744924B2 (ja) |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4301383A (en) * | 1979-10-05 | 1981-11-17 | Harris Corporation | Complementary IGFET buffer with improved bipolar output |
JPH02183178A (ja) * | 1989-01-09 | 1990-07-17 | Toshiba Corp | 半導体装置 |
JP2504287B2 (ja) * | 1990-05-18 | 1996-06-05 | 日本電気株式会社 | 多層配線基板 |
JPH0422886A (ja) * | 1990-05-18 | 1992-01-27 | Nissan Motor Co Ltd | 半導体入出力回路 |
US5220483A (en) * | 1992-01-16 | 1993-06-15 | Crystal Semiconductor | Tri-level capacitor structure in switched-capacitor filter |
JPH06274241A (ja) * | 1993-03-18 | 1994-09-30 | Fujitsu Ltd | 半導体基板上のクロック分配方式 |
US5754066A (en) * | 1996-06-19 | 1998-05-19 | Maxim Integrated Products | Output stage for buffering an electrical signal and method for performing the same |
JPH10107211A (ja) | 1996-10-01 | 1998-04-24 | Kawasaki Steel Corp | テスト容易化回路 |
US6002287A (en) * | 1997-05-08 | 1999-12-14 | Canon Kabushiki Kaisha | Signal outputting apparatus |
JP3328553B2 (ja) | 1997-07-25 | 2002-09-24 | 松下電器産業株式会社 | 回路基板検査装置 |
JP4033275B2 (ja) | 1998-10-23 | 2008-01-16 | 株式会社ルネサステクノロジ | 半導体集積回路装置 |
EP1071130A3 (en) * | 1999-07-14 | 2005-09-07 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device interconnection structure comprising additional capacitors |
JP3337013B2 (ja) | 1999-09-20 | 2002-10-21 | 日本電気株式会社 | 大規模集積回路の非接触計測装置 |
JP2001116805A (ja) * | 1999-10-20 | 2001-04-27 | Nec Corp | Lsiパッケージ |
US6807109B2 (en) * | 2001-12-05 | 2004-10-19 | Renesas Technology Corp. | Semiconductor device suitable for system in package |
-
2005
- 2005-05-10 JP JP2005137391A patent/JP4744924B2/ja not_active Expired - Fee Related
-
2006
- 2006-05-01 US US11/415,584 patent/US7805646B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US7805646B2 (en) | 2010-09-28 |
JP2006317170A (ja) | 2006-11-24 |
US20060255661A1 (en) | 2006-11-16 |
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