JP4724652B2 - アンダーフィル薄膜を有する印刷配線アセンブリ - Google Patents

アンダーフィル薄膜を有する印刷配線アセンブリ Download PDF

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Publication number
JP4724652B2
JP4724652B2 JP2006503178A JP2006503178A JP4724652B2 JP 4724652 B2 JP4724652 B2 JP 4724652B2 JP 2006503178 A JP2006503178 A JP 2006503178A JP 2006503178 A JP2006503178 A JP 2006503178A JP 4724652 B2 JP4724652 B2 JP 4724652B2
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Japan
Prior art keywords
package
circuit board
printed circuit
array
underfill adhesive
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
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JP2006503178A
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English (en)
Japanese (ja)
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JP2006517348A5 (enExample
JP2006517348A (ja
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ダンビル、ジャニス
デバニー、キャサリン
ヤラ、ナディア
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NXP USA Inc
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NXP USA Inc
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Publication of JP2006517348A publication Critical patent/JP2006517348A/ja
Publication of JP2006517348A5 publication Critical patent/JP2006517348A5/ja
Application granted granted Critical
Publication of JP4724652B2 publication Critical patent/JP4724652B2/ja
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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/303—Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
    • H05K3/305—Affixing by adhesive
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/28—Applying non-metallic protective coatings
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K7/00—Constructional details common to different types of electric apparatus
    • H05K7/02—Arrangements of circuit components or wiring on supporting structure
    • H05K7/10—Plug-in assemblages of components, e.g. IC sockets
    • H05K7/1053—Plug-in assemblages of components, e.g. IC sockets having interior leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/2901—Shape
    • H01L2224/29012—Shape in top view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/2901—Shape
    • H01L2224/29012—Shape in top view
    • H01L2224/29015—Shape in top view comprising protrusions or indentations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/30—Structure, shape, material or disposition of the layer connectors prior to the connecting process of a plurality of layer connectors
    • H01L2224/301—Disposition
    • H01L2224/3012—Layout
    • H01L2224/3015—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/30—Structure, shape, material or disposition of the layer connectors prior to the connecting process of a plurality of layer connectors
    • H01L2224/301—Disposition
    • H01L2224/3012—Layout
    • H01L2224/3015—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
    • H01L2224/30154—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry covering only portions of the surface to be connected
    • H01L2224/30155—Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3205—Shape
    • H01L2224/32057—Shape in side view
    • H01L2224/32058—Shape in side view being non uniform along the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/731—Location prior to the connecting process
    • H01L2224/73101—Location prior to the connecting process on the same surface
    • H01L2224/73103—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0104—Properties and characteristics in general
    • H05K2201/0129—Thermoplastic polymer, e.g. auto-adhesive layer; Shaping of thermoplastic polymer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09909—Special local insulating pattern, e.g. as dam around component
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10734—Ball grid array [BGA]; Bump grid array
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/01—Tools for processing; Objects used during processing
    • H05K2203/0191—Using tape or non-metallic foil in a process, e.g. during filling of a hole with conductive paste
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Non-Metallic Protective Coatings For Printed Circuits (AREA)
JP2006503178A 2003-01-31 2004-01-30 アンダーフィル薄膜を有する印刷配線アセンブリ Expired - Lifetime JP4724652B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10/356,419 2003-01-31
US10/356,419 US7265994B2 (en) 2003-01-31 2003-01-31 Underfill film for printed wiring assemblies
PCT/US2004/002615 WO2004071140A2 (en) 2003-01-31 2004-01-30 Underfill film for printed wiring assemblies

Publications (3)

Publication Number Publication Date
JP2006517348A JP2006517348A (ja) 2006-07-20
JP2006517348A5 JP2006517348A5 (enExample) 2007-03-15
JP4724652B2 true JP4724652B2 (ja) 2011-07-13

Family

ID=32770803

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006503178A Expired - Lifetime JP4724652B2 (ja) 2003-01-31 2004-01-30 アンダーフィル薄膜を有する印刷配線アセンブリ

Country Status (5)

Country Link
US (1) US7265994B2 (enExample)
JP (1) JP4724652B2 (enExample)
KR (1) KR101054239B1 (enExample)
CN (1) CN100524707C (enExample)
WO (1) WO2004071140A2 (enExample)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20020053326A (ko) * 2000-12-27 2002-07-05 이일희 폐옥을 이용한 건축자재 제조방법
KR100475540B1 (ko) * 2002-05-27 2005-03-10 양원모 건축물 마감재의 제조 방법
US7004375B2 (en) 2003-05-23 2006-02-28 National Starch And Chemical Investment Holding Corporation Pre-applied fluxing underfill composition having pressure sensitive adhesive properties
US6978540B2 (en) 2003-05-23 2005-12-27 National Starch And Chemical Investment Holding Corporation Method for pre-applied thermoplastic reinforcement of electronic components
CN100499101C (zh) * 2006-08-02 2009-06-10 南茂科技股份有限公司 具有延长引脚的薄膜覆晶封装构造
US7889959B2 (en) * 2008-02-07 2011-02-15 Lockheed Martin Corporation Composite material for cable floatation jacket
JP2010103336A (ja) * 2008-10-24 2010-05-06 Fujitsu Ltd 基板ユニット、情報処理装置及び基板ユニットの製造方法
US20110115099A1 (en) * 2009-05-14 2011-05-19 Vertical Circuits, Inc. Flip-chip underfill
KR20110024291A (ko) * 2009-09-01 2011-03-09 삼성전기주식회사 회로 기판, 반도체 패키지 및 회로 기판의 제조 방법
US20110067910A1 (en) * 2009-09-18 2011-03-24 International Business Machines Corporation Component securing system and associated method
US10429929B2 (en) 2010-09-24 2019-10-01 Blackberry Limited Piezoelectric actuator apparatus and methods
FR2994768B1 (fr) 2012-08-21 2016-02-05 Commissariat Energie Atomique Hybridation face contre face de deux composants microelectroniques a l'aide d'un recuit uv
US20150064851A1 (en) * 2013-09-03 2015-03-05 Rohm And Haas Electronic Materials Llc Pre-applied underfill
KR20170064594A (ko) 2015-12-01 2017-06-12 삼성디스플레이 주식회사 전자 소자의 실장 방법 및 이에 사용되는 언더 필 필름
CN107025481B (zh) * 2016-02-02 2021-08-20 上海伯乐电子有限公司 柔性印制电路板及应用其的智能卡模块和智能卡
KR102694680B1 (ko) 2016-08-01 2024-08-14 삼성디스플레이 주식회사 전자 소자, 이의 실장 방법 및 이를 포함하는 표시 장치의 제조 방법
US11153970B1 (en) * 2020-07-20 2021-10-19 Atl Technology, Llc Apparatus with electrical components end mounted to printed circuit board
CN113438826B (zh) * 2021-06-29 2022-10-28 荣成歌尔微电子有限公司 底填胶封装方法及设备

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5859470A (en) * 1992-11-12 1999-01-12 International Business Machines Corporation Interconnection of a carrier substrate and a semiconductor device
GB9502178D0 (en) * 1995-02-03 1995-03-22 Plessey Semiconductors Ltd MCM-D Assemblies
US5836715A (en) * 1995-11-19 1998-11-17 Clark-Schwebel, Inc. Structural reinforcement member and method of utilizing the same to reinforce a product
JPH1084014A (ja) * 1996-07-19 1998-03-31 Shinko Electric Ind Co Ltd 半導体装置の製造方法
US5796169A (en) * 1996-11-19 1998-08-18 International Business Machines Corporation Structurally reinforced ball grid array semiconductor package and systems
JPH10163386A (ja) * 1996-12-03 1998-06-19 Toshiba Corp 半導体装置、半導体パッケージおよび実装回路装置
US6333206B1 (en) * 1996-12-24 2001-12-25 Nitto Denko Corporation Process for the production of semiconductor device
JP3604248B2 (ja) * 1997-02-25 2004-12-22 沖電気工業株式会社 半導体装置の製造方法
US6040630A (en) * 1998-04-13 2000-03-21 Harris Corporation Integrated circuit package for flip chip with alignment preform feature and method of forming same
US6139705A (en) * 1998-05-06 2000-10-31 Eltech Systems Corporation Lead electrode
US6426566B1 (en) * 1998-12-02 2002-07-30 Seiko Epson Corporation Anisotropic conductor film, semiconductor chip, and method of packaging
US6657313B1 (en) * 1999-01-19 2003-12-02 International Business Machines Corporation Dielectric interposer for chip to substrate soldering
US6291899B1 (en) * 1999-02-16 2001-09-18 Micron Technology, Inc. Method and apparatus for reducing BGA warpage caused by encapsulation
JP3447620B2 (ja) * 1999-07-05 2003-09-16 Ｎｅｃエレクトロニクス株式会社 フリップチップ実装型半導体装置の製造方法
JP3654116B2 (ja) * 2000-03-10 2005-06-02 セイコーエプソン株式会社 半導体装置及びその製造方法、回路基板並びに電子機器
US6570259B2 (en) * 2001-03-22 2003-05-27 International Business Machines Corporation Apparatus to reduce thermal fatigue stress on flip chip solder connections
US20020162679A1 (en) * 2001-05-04 2002-11-07 Nael Hannan Package level pre-applied underfills for thermo-mechanical reliability enhancements of electronic assemblies
JP4417596B2 (ja) * 2001-09-19 2010-02-17 富士通株式会社 電子部品の実装方法
US6696748B1 (en) * 2002-08-23 2004-02-24 Micron Technology, Inc. Stress balanced semiconductor packages, method of fabrication and modified mold segment
US6877964B2 (en) * 2002-11-06 2005-04-12 The United States Of America As Represented By The Secretary Of The Air Force Multifunction microfluidics device

Also Published As

Publication number Publication date
WO2004071140A2 (en) 2004-08-19
WO2004071140A3 (en) 2005-04-28
US20040150967A1 (en) 2004-08-05
US7265994B2 (en) 2007-09-04
KR101054239B1 (ko) 2011-08-08
CN100524707C (zh) 2009-08-05
CN1742369A (zh) 2006-03-01
JP2006517348A (ja) 2006-07-20
KR20050092456A (ko) 2005-09-21

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